參數(shù)資料
型號： TMC2072KHC
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 消費家電
英文描述： Genlocking Video Digitizer
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： MQFP-100
文件頁數(shù)： 12/21頁
文件大?。?/td> 160K
代理商： TMC2072KHC
TMC2072
PRODUCT SPECIFICATION
12
REV. 1.0.4 6/19/01
Horizontal Timing
Horizontal line rate is determined by the V_STD control bits.
Figure 4 illustrates the horizontal blanking interval. Figure 5
completes the definition of timing parameters with vertical
blanking interval detail.
Figure 4. Horizontal Sync Timing
Figure 5. Vertical Sync timing
Programming the TMC2072
Upon power-up after bringing RESET LOW, the TMC2072
Control Register is set to default values listed previously.
These default values do not necessarily render the TMC2072
operational in any specific application. Before the TMC2072
is expected to acquire input video, its Control Register must
be loaded with control values specific to its use.
65-2072-06
Video In
Burst
GHSYNC
tDH
H
2.35
μ
sec PAL
2.3
μ
sec NTSC
Equalizing Pulse
tDH
tVD
0.5H
4.7
μ
sec
Serration
Video In
65-2072-07
GVSYNC
GHSYNC
(Odd Field)
GHSYNC
(Even Field)
Table 2. TMC2072 Timing Options
*TMC2072-1 only
Table 3. Control Register Example Data
Assumptions: Clean 1-volt (sync to ref white) signal on V
IN1
.
All other control registers left in power-up states.
Standard
NTSC, PAL-M
NTSC-D1
PAL-D1
PAL-VGA*
PAL-VGA*
Field
Rate (Hz)
59.94
59.94
50.00
50.0
50.0
Line
Rate (kHz)
15.734264
15.734264
15.625
15.625
15.625
Pixel
Rate (Mpps)
12.2727+
13.50
13.50
14.75
15.0
PXCK
Frequency (MHz)
24.54+
27.0
27.0
29.0
30.0
Plxels
Per Line
780
858
864
944
960
Register
8
D
E
Value
10h
03h
08h
Function
13.5 MHz Pixel Rate
Sync tip = 3
Enable Outputs
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