參數(shù)資料
型號: TMC2192KHC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 顏色信號轉(zhuǎn)換
英文描述: 10 Bit Encoder
中文描述: COLOR SIGNAL ENCODER, PQFP100
封裝: MQFP-100
文件頁數(shù): 3/69頁
文件大小: 457K
代理商: TMC2192KHC
PRODUCT SPECIFICATION
TMC2192
REV. 1.0.0 8/13/03
3
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Input Formats . . . . . . . . . . . . . . . . . . . . . .7
24 bit Input Format . . . . . . . . . . . . . . . . . .7
CCIR656 Input Format . . . . . . . . . . . . . . .8
10 bit Input Format . . . . . . . . . . . . . . . . . .8
20 bit 4:2:2 Input Format . . . . . . . . . . . . .8
20 bit 4:4:4 Input Format . . . . . . . . . . . . .8
Propagation Delay through the
Encoder . . . . . . . . . . . . . . . . . . . . . . . . .10
Horizontal Timing . . . . . . . . . . . . . . . . . .13
Horizontal Timing – Vertical Blanking . . .13
Figure 10. Horizontal Timing – 1st Half-line. . . . . . .14
Figure 11. Horizontal Timing – 2nd Half-line . . . . . .14
Figure 12. NTSC Vertical Interval . . . . . . . . . . . . . .15
Figure 13. PAL Vertical Interval . . . . . . . . . . . . . . . .17
Figure 14. PAL-M Vertical Interval . . . . . . . . . . . . . .19
Figure 15. Burst Envelope . . . . . . . . . . . . . . . . . . . .23
Figure 16. Gaussian Filter Response . . . . . . . . . . .23
Figure 17. Interpolation Filter. . . . . . . . . . . . . . . . . .25
Figure 18. Interpolation Filter – Passband
Detail . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 19. X/SIN(X) Filter . . . . . . . . . . . . . . . . . . . .25
Figure 20. Layering Engine . . . . . . . . . . . . . . . . . . .28
Figure 21. Overlay Outputs . . . . . . . . . . . . . . . . . . .29
Figure 22. Data Keying . . . . . . . . . . . . . . . . . . . . . .29
Figure 23. Microprocessor Parallel Port –
Write Timing . . . . . . . . . . . . . . . . . . . . . .30
Figure 24. Microprocessor Parallel Port –
Read Timing . . . . . . . . . . . . . . . . . . . . . .30
Figure 25. Serial Port Read/Write Timing . . . . . . . .31
Figure 26. Serial Interface – Typical Byte
Transfer. . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 27. Serial Interface – Chip Address . . . . . . .32
Figure 28. Typical Analog Reconstruction Filter . . .63
Figure 29. Overall Response. . . . . . . . . . . . . . . . . .63
Figure 30. Typical Layout. . . . . . . . . . . . . . . . . . . . .65
Figure 31. ST-163E Layout . . . . . . . . . . . . . . . . . . .66
Figure 32. Pass Band . . . . . . . . . . . . . . . . . . . . . . .67
Figure 33. Stop Band. . . . . . . . . . . . . . . . . . . . . . . .67
Figure 34. 2T Pulse . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 35. Group Delay . . . . . . . . . . . . . . . . . . . . . .67
Figure 8.
Figure 9.
List of Tables
Table 1.
Table 2.
CSM Coefficient Range . . . . . . . . . . . . . 9
Expected Output Values for the
CSM with YCBCR Inputs . . . . . . . . . . . . 9
PDC Edge Control . . . . . . . . . . . . . . . . 11
Horizontal Line Equations. . . . . . . . . . . 12
Horizontal Timing Specifications. . . . . . 13
Vertical Interval Timing
Specifications . . . . . . . . . . . . . . . . . . . . 14
Default Horizontal Timing
Parameters. . . . . . . . . . . . . . . . . . . . . . 15
NTSC Field/Line Sequence and
Identification . . . . . . . . . . . . . . . . . . . . . 16
PAL Field/Line Sequence and
Identification . . . . . . . . . . . . . . . . . . . . . 18
PAL-M Field/Line Sequence and
Identification . . . . . . . . . . . . . . . . . . . . . 20
Standard Subcarrier Parameters . . . . . 22
Line by Line Pedestal Enable . . . . . . . . 23
Closed Caption Line Selection . . . . . . . 24
D/A Outputs . . . . . . . . . . . . . . . . . . . . . 25
Ancillary Data Format. . . . . . . . . . . . . . 26
Ancillary Data Control – Phase . . . . . . 27
Ancillary Data Control Frequency. . . . . 27
Field Identification and Subcarrier
Reset Modes . . . . . . . . . . . . . . . . . . . . 27
Layering and Keying Modes . . . . . . . . . 28
Overlay Address Map. . . . . . . . . . . . . . 29
Parallel Port Control . . . . . . . . . . . . . . . 30
Serial Port Addresses. . . . . . . . . . . . . . 31
Control Register Map . . . . . . . . . . . . . . 33
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
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