參數(shù)資料
型號(hào)： TMC2272A
廠商： Fairchild Semiconductor Corporation
英文描述： 36 Bit Color, 50 MHz Digital Colorspace Converter(36位色彩,50MHz 數(shù)字色隙轉(zhuǎn)換器)
中文描述： 36位彩色，50兆赫數(shù)字色空間轉(zhuǎn)換器（36位色彩，50MHz的數(shù)字色隙轉(zhuǎn)換器）
文件頁(yè)數(shù)： 3/20頁(yè)
文件大?。?/td> 170K
代理商： TMC2272A
TMC2272A
PRODUCT SPECIFICATION
REV. 1.1.3 10/25/00
3
Pin Assignments
120 Pin Plastic Pin Grid Array, H5 Package, 120 Pin Ceramic Pin Grid Array, G1 Package, and
120 Pin MQFP to PPGA, H6 Package
B
A
D
E
F
G
H
J
K
L
M
N
C
1
2
3
4
5
6
7
8
9
10
11
12
13
Top View
Cavity Up
KEY
X7
X9
X10
GND
C11
C8
C7
C5
C3
C1
B10
B7
B4
X4
X5
X8
X11
GND
C9
C6
C4
C2
B11
B9
B6
B2
X1
X2
X6
VDD
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
C1
C2
C3
C4
GND
C10
GND
VDD
C0
B8
B5
B3
B1
Y11
X0
X3
CLK
B0
A10
Y9
Y10
GND
A11
A9
A8
Y7
Y8
VDD
A7
A6
A5
Y5
Y6
GND
C5
C6
C7
C8
C9
C10
C11
C12
C13
D1
D2
D3
D11
D12
D13
E1
E2
E3
E11
E12
E13
F1
F2
F3
F11
F12
F13
G1
G2
G3
Pin
Name
Pin
Name
A3
A2
A4
Y4
Y0
VDD
GND
A0
A1
Y1
Y2
GND
KA8
CWSEL1
CWSEL0
Y3
Z0
Z3
KA4
KA7
KA9
Z1
Z4
Z6
GND
KC0
GND
VDD
KB0
KB4
G11
G12
G13
H1
H2
H3
H11
H12
H13
J1
J2
J3
J11
J12
J13
K1
K2
K3
K11
K12
K13
L1
L2
L3
L4
L5
L6
L7
L8
L9
KB8
KA1
KA5
KA6
Z2
Z7
Z9
Z11
KC2
KC4
KC6
KC9
KB2
KB5
KB9
KA2
KA3
Z5
Z8
Z10
KC1
KC3
KC5
KC7
KC8
KB1
KB3
KB6
KB7
KA0
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
Pin
Name
Pin
Name
Functional Description
The TMC2272A is a nine–multiplier array with the internal bus
structure and summing adders needed to implement a 3 x 3
matrix multiplier (triple dot product). With a 50MHz guaran-
teed maximum clock rate, this device offers video and imaging
system designers a single–chip solution to numerous common
image and signal–processing problems.
The three data input ports (A
two's complement integer data, which is also the format for
the output ports (X
11-0
, Y
11-0
, Z
width options are discussed in the numeric format and over-
flow section. The coefficient input ports (KA, KB, KC) are
always 10-bit two's complement fractional. Table
the bit weighting.
11-0
, B
11-0
, C
11-0
) accept 12-bit
11-0
). Other format and path
2
details
Full precision is maintained throughout the TMC2272A.
Each output is accurately rounded to 12 bits from the 23 bits
entering the final adder.
Signal Definitions
A(n), B(n), C(n)
Indicates the data word presented to that input
port during the specified clock rising edge (n).
Applies to input ports A
11-0
, B
11-0
, and C
11-0
.
KAX(n) thru KCZ(n)
Indicates coefficient value stored in the specified
one of the nine onboard coefficient registers
KAX through KCZ, input during or before the
specified clock rising edge (n).
X(n), Y(n), Z(n)
Indicates data available at that output port t
after the specified clock rising edge (n).
Applies to output ports X
DO
11-0
, Y
11-0
, and Z
11-0
.
The TMC2272A utilizes six input and output ports to realize
a "triple dot product", in which each output is the sum of all
three input words, multiplied by the appropriate stored coef-
ficients. The three corresponding sums of products are avail-
able at the outputs five clock cycles after the input data are
latched, and three new data words rounded to 12-bits are then
available every clock cycle. See the Applications Discussion
regarding encoded video standard conversion matrices.
X(5)=A(1)KAX(1)+B(1)KBX(1)+C(1)KCX(1)
Y(5)=A(1)KAY(1)+B(1)KBY(1)+C(1)KCY(1)
Z(5)=A(1)KAZ(1)+B(1)KBZ(1)+C(1)KCZ(1)
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