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參數(shù)資料
| 型號： | TMC22X5YA |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| 中文描述： | 多標準數(shù)字視頻解碼器三線自適應梳狀解碼器系列，8 |
| 文件頁數(shù)： | 31/84頁 |
| 文件大?。?/td> | 417K |
| 代理商： | TMC22X5YA |
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PRODUCT SPECIFICATION
TMC22x5yA
REV. 1.0.0 2/4/03
31
Control Register De
fi
nitions
(continued)
Buffered register set 1 (29)
Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
UG1
7
UG1
6
UG1
5
UG1
4
UG1
3
UG1
2
UG1
1
UG1
0
Reg
29
Bit
7-0
Name
UG1
7-0
Description
U gain, 8 lsbs.
Bottom 8 bits of the U gain
lsb = 1/256
Buffered register set 1 (2A)
Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
VG1
7
VG1
6
VG1
5
VG1
4
VG1
3
VG1
2
VG1
1
VG1
0
Reg
2A
Bit
7-0
Name
VG1
7-0
Description
V gain, 8 lsbs.
Bottom 8 bits of the V gain
lsb = 1/256
Buffered register set 1 (2B)
Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
YG1
9
YG1
8
UG1
10
UG1
9
UG1
8
Reserved
VG1
9
VG1
8
Reg
2B
Bit
7-6
Name
YG1
9-8
Description
Y gain, 2 msbs.
Top 2 bits of the Y gain
msb = 2
U gain, 3 msbs.
Top 3 bits of the U gain.
msb = 4
reserved, set to zero
V gain, 2 msbs.
Top 2 bits of the V gain
msb = 2
2B
5-3
UG1
10-8
2B
2B
2
1-0
Reserved
VG1
9-8
Buffered register set 1 (2C)
Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
YOFF1
7
YOFF1
6
YOFF1
5
YOFF1
4
YOFF1
3
YOFF1
2
YOFF1
1
YOFF1
0
Reg
2C
Bit
7-0
Name
YOFF1
7-0
Description
Y offset, 8 lsbs.
Bottom 8 bits of luma or RGB offset
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