參數(shù)資料
型號： TMC2302AH5C
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 數(shù)字信號處理外設(shè)
英文描述： Image Manipulation Sequencer
中文描述： 16-BIT, DSP-ADDRESS SEQUENCER, PPGA120
封裝： CAVITY-UP, PLASTIC, PGA-120
文件頁數(shù)： 9/36頁
文件大?。?/td> 188K
代理商： TMC2302AH5C
PRODUCT SPECIFICATION
TMC2302A
9
P
TWR
N6
43
Target Memory Write Enable.
interpolation walk, the Target Write Enable goes LOW for one clock
cycle, returning HIGH for all but the last cycle of the next walk.
When performing nearest-neighbor resampling, this control will
remain LOW throughout the entire transform. This output can be
forced to the high-impedance state by the enable control OET, and
can be delayed up to seven clock cycles after the nominal
sequence shown in Table 4 by the pipe-line delay parameter
PIPTWR. See the Device Configuration and Control Parameters
section.
No Operation.
Assuming that INIT remains LOW, the internal
system clock of the TMC2302A will be disabled on the next clock,
halting the current transform, when the registered control input
NOOP goes LOW. When NOOP returns HIGH, normal operation
resumes on the next clock. This control does not affect the loading
of the configuration and transformation parameter preread
registers.
Source Address Output Enable.
SADR
23-0
is enabled when the asynchronous output enable OES
is LOW. When OES is HIGH, the port is in the high-impedance
state.
Coefficient Address Output Enable.
address port KADR
7-0
is enabled when the asynchro- nous output
enable OEK is LOW. When OEK is HIGH, the port is in the high-
impedance state.
Target Address Output Enable.
and target write enable TWR are enabled when the
asynchronous Target Output Enable OET is LOW. When OET is
HIGH, these outputs are in the high-impedance state. This control
functions in both the normal and extended addressing modes.
On the last cycle of each
NOOP
L13
66
OES
A6
108
The source address port
OEK
M2
31
The interpolation coefficient
OET
M6
42
The target address port TADR
11-
0
Flags
SVAL
L1
26
Source Address Valid.
component output is within the working space defined by the
parameters XMIN and XMAX (or YMIN, YMAX for the column (Y/V)
device or ZMIN, ZMAX for the page (Z/W) device), the Source
Address Valid flag SVAL for that device is LOW. This flag will go
HIGH on the clock in which the corresponding component address
falls outside the defined region. In a typical system, the SVAL
outputs of all IMS devices are OR’ed together to generate a global
boundary violation flag. The user might then insert zeroes into the
pixel interpolator to ignore that portion of the image outside the
defined space, or insert a background color or image. This output
can be delayed up to seven clock cycles after the nominal
sequence shown in Table 4 by the pipeline delay parameter
PIPSVA. See the Device Configuration and Control Parameters
section.
When the current source image address
Pin Descriptions
(continued)
Pin Name
Pin Number
PPGA
Pin Function Description
MQFP
相關(guān)PDF資料
PDF描述
TMC2302AH5C1 Image Manipulation Sequencer
TMC2302AKEC Image Manipulation Sequencer
TMC2302AKEC1 Image Manipulation Sequencer
TMC2330AH5C Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330AH5C1 Coordinate Transformer 16 x 16 Bit, 40 MOPS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMC2302AH5C1 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述:
TMC2302AKEC 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer
TMC2302AKEC1 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer
TMC2330A 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330AG1C 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS
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