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參數(shù)資料
| 型號： | TMC2490 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Digital Video Encoders(數(shù)字視頻編碼器) |
| 中文描述： | 數(shù)字視頻編碼器（數(shù)字視頻編碼器） |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 173K |
| 代理商： | TMC2490 |
TMC2063
PRODUCT SPECIFICATION
2
The board accepts 8-bit parallel digital component video,
(CCIR Rec. 656 or SMPTE RP 125, a.k.a. “D1”) at a stan-
dard D25 connector in differential ECL format and translates
the data to TTL format. The TMC2490 accepts the multi-
plexed D1 data stream and internally strips the Timing
Reference Signal (TRS) to produce the required horizontal
and vertical references. The D1 data for the TMC22091 is
externally processed to strip the Timing Reference Signal
from the data stream to generate H&V Sync, and is demulti-
plexed to pass the digital video stream to the Encoder in a
16-bit 13.5 MHz format. The TMC2490 may also be
operated in Master Mode by interfacing the Pixel Data (PD)
bus through header JP1.
A simple EPROM-based programmer is provided, which
downloads the selected configuration (one of 64) to the two
digital Encoders when the reset button is pressed, through
the parallel microprocessor interface. This EPROM holds
both control register data and Color-Look-Up-Table (CLUT)
patterns in 1K blocks. Sixteen pages are selected by a rotary
switch, and additional switches are provided for selecting the
required video standard.
The board operates from standard
in stand-alone mode, only +5V is required.
±
5V supplies. When used
CCIR-601 Interface
The CCIR-601 data stream is terminated into differential
ECL-to-TTL converters. The translated data is latched
through U16 at a 27 MHz rate and then passed directly to the
TMC2490, the YC demultiplexer, and the TRS decoder. The
TMC2490 locks the internal state machines to the TRS
words embedded in the D1 data stream. The horizontal state
machine produces the control signals required to separate the
CbYCr[Y] data and interpolate the CbCr color difference
signals to the luminance sample rate. For the TMC22091,
the luminance and chrominance data words are separated
into two data streams termed Y and C, respectively, exter-
nally in the YC demultiplexer. This YC data goes directly
into the TMC22091, which separates the C data stream into
its two color difference signals and interpolates them to the
same sample rate as Y data. This interpolation, as in the
TMC2490, improves the horizontal color definition.
The TRS decoder extracts the field (F), vertical blanking (V),
and horizontal blanking (H) information from the D1 data
stream for use in the timing signal generation on the board.
The TRS decoder also produces the pixel counter reset and
the LDV signal for latching the YC data into the TMC22091.
Master Mode Interface
A MASTER mode pixel data bus is available on header JP1.
In the default slave mode, pins 25 and 26 are left uncon-
nected. The PD port of the TMC2490 receives its input from
the ECL to TTL slave interface. By connecting pins 25 and
26 the TMC2490 receives the pixel data (PD) from the
header JP1. In addition, all synchronization pins are con-
nected to JP1 which allows access to these pins when the
TMC2490 operates in a MASTER mode.
Horizontal and Vertical Timing for the
TMC22091
The pixel counter (U3, U11, and U2) is decoded to produce
the VHSYNC and PDC signals required by the TMC22091
in Slave Mode for horizontal synchronization. A 2x line rate
clock, H/2_CLK, used in the VVSYNC generation, is also
produced along with P_CLOCK and DATA_EN. P_CLOCK
is used to clock the program counters and the DATA_EN
signal used in the YC demultiplexing circuit.
A 4-bit counter embedded in U8 is started whenever V goes
HIGH, which occurs at the beginning of each vertical blank-
ing interval. This counter is clocked by H/2_CLK, which
enables the VVSYNC pulse to be produced at the same time
as the first vertical sync pulse in each field. The PGM output
signal ensures that the software reset signal, RES_OUT, goes
HIGH 15 half-line periods before the program counter starts.
Software Reset
A software reset occurs whenever the pushbutton switch, S2,
is depressed. The software reset is latched through U8 to
ensure a known relationship between the internal pixel clock
of the external PXCK clock in master mode. When S2 is
depressed the internal state machines of the TMC22091 and
TMC2490 are reset and the outputs are disabled. When S2 is
released the program counter is started at the beginning of
the next vertical blanking period, when a D1 input is
provided, or immediately if the TMC22091 is being
programmed to produce master mode test patterns. Software
Reset is required after power-up and after each functional
change.
Programming the TMC22091 and TMC2490
A 12-bit counter (U1, U9, and U10) is used to produce the
addresses used in programming the TMC22091 and
TMC2490. U13 produces the required R/W, A1:0, and CS
signals for the TMC22091 while U17 produces the R/W,
ADR, and CS required by the TMC2490. The EPROM,
U22, contains 32 different pages of setup data for NTSC and
another 32 pages for PAL (selected via switch S3). Switch
E4 selects between different flavors of NTSC and PAL oper-
ation. To ensure that the outputs of the programmable logic
(U13 and U17) are correctly timed to transitions on the
microprocessors data bus, they are addressed at four times
the rate that U22 is addressed. The 16 pages of setup data
are selected by the rotary switch S1, as shown in Table 1.
The TMC2490 produces an internal ramp pattern for rotary
switch positions 0, 1, and 2 and encodes the D1 input data
for positions 3 through F.
The programming of the encoder operation into each of the
64 memory pages by banks of 16 by video standard (Table 2)
is entirely arbitrary: one could as easily assign CCIR-601
operation in the four supported formats to pages 0-3, and
color bars to pages 4-7. The user is encouraged to replace
the EPROM with one programmed with other formats of
interest.
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| TMC2490AR2CT | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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