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參數(shù)資料
| 型號： | TMC2491A |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multistandard Digital Video Encoder(多標準數(shù)字視頻編碼器) |
| 中文描述： | 多標準數(shù)字視頻編碼器（多標準數(shù)字視頻編碼器） |
| 文件頁數(shù)： | 23/36頁 |
| 文件大小： | 208K |
| 代理商： | TMC2491A |
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PRODUCT SPECIFICATION
TMC2490A/TMC2491A
23
Serial Control Port (R-Bus)
In addition to the 11-wire parallel port, a 2-wire serial con-
trol interface is also provided, and active when SER is LOW.
Either port alone can control the entire chip. Up to four
TMC2490(1)A devices may be connected to the 2-wire
serial interface with each device having a unique address.
The 2-wire interface comprises a clock (SCL/CS) and a bi-
directional data (SDA/R/W) pin. The TMC2490(1)A acts as
a slave for receiving and transmitting data over the serial
interface. When the serial interface is not active, the logic
levels on SCL/CS and SDA/R/W are pulled HIGH by exter-
nal pull-up resistors.
Data received or transmitted on the SDA/R/W line must be
stable for the duration of the positive-going SCL/CS pulse.
Data on SDA/R/W can only change when SCL/CS is LOW.
If SDA/R/W changes state while SCL/CS is HIGH, the serial
interface interprets that action as a start or stop sequence.
There are five components to serial bus operation:
Start signal
Slave address byte
Base register address byte
Data byte to read or write
Stop signal
When the serial interface is inactive (SCL/CS and
SDA/R/W are HIGH) communications are initiated by send-
ing a start signal. The start signal is a HIGH-to-LOW transi-
tion on SDA/R/W while SCL/CS is HIGH. This signal alerts
all slaved devices that a data transfer sequence is coming.
The first eight bits of data transferred after a start signal com-
prise a seven bit slave address and a single R/W bit. As
shown in Figure 16A, the R/W bit indicates the direction of
data transfer, read from or write to the slave device. If the
transmitted slave address matches the address of the device
(set by the state of the SA
0
/ADR and SA
1
input pins in Table
15), the TMC2490(1)A acknowledges by bringing SDA/R/
W LOW on the 9th SCL/CS pulse. If the addresses do not
match, the TMC2490(1)A does not acknowledge.
Figure 13. Microprocessor Parallel Port - Write Timing
Figure 14. Microprocessor Parallel Port - Read Timing
t
PWLCS
t
HA
t
SA
t
HD
t
SD
t
PWHCS
SCL/
CS
SA
0
/ADR
65-3548-02
SDA / R/
W
D
7-0
t
SA
t
DOM
t
DOZ
t
HA
t
HOM
t
PWLCS
t
PWHCS
SCL/
CS
SA
0
/ADR
65-3548-03
SDA / R/
W
D
7-0
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