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參數(shù)資料
| 型號： | TMC3003KR2C30 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | TRIPLE, PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 10-BIT DAC, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 68K |
| 代理商： | TMC3003KR2C30 |
TMC3003
PRODUCT SPECIFICATION
4
Pin Descriptions
Pin Name
Pin Number
Value
Description
PLCC
LQFP
Clock and Pixel I/O
CLK
29
26
TTL
Clock. The clock input is TTL-compatible and all pixel data
is registered on the rising edge of CLK. It is recommended
that CLK be driven by a dedicated TTL buffer to avoid
reflection induced jitter, overshoot, and undershoot.
R9-0
5, 4, 3, 2, 1,
44, 43, 42,
41, 40
47, 46, 45,
44, 43, 42,
41, 40, 39,
38, 37
TTL
Red pixel data inputs. The Red digital input is TTL-
compatible and registered on the rising edge of CLK.
G9-0
15, 14, 13,
12, 11, 10, 9,
8, 7, 6
48, 9, 8, 7, 6,
5, 4, 3, 2, 1
TTL
Green pixel data inputs. The Green digital input is TTL-
compatible and registered on the rising edge of CLK.
B9-0
28, 27, 26,
25, 24, 23,
22, 21, 20,
19
23, 22, 21,
20, 19, 18,
17, 16, 15,
14
TTL
Blue pixel data inputs. The Blue digital input is TTL-
compatible and registered on the rising edge of CLK.
Controls
SYNC
17
11
TTL
Sync pulse Input. Bringing SYNC LOW, turns off a 40
IRE (7.62 mA) current source which forms a sync pulse on
the Green D/A converter output. SYNC is registered on the
rising edge of CLK along with pixel data and has the same
pipeline latency as BLANK and pixel data. SYNC does not
override any other data and should be used only during
the blanking interval.
Since this is a single-supply D/A and all signals are
positive-going, sync is added to the bottom of the Green
D/A range. So turning SYNC OFF means turning the
current source ON. When a sync pulse is desired, the
current source is turned OFF. If the system does not
require sync pulses from the Green D/A converter, SYNC
should be connected to GND.
BLANK
16
10
TTL
Blanking Input. When BLANK is LOW, pixel inputs are
ignored and the D/A converter outputs are driven to the
blanking level. BLANK is registered on the rising edge of
CLK and has the same pipeline latency as SYNC.
Video Outputs
IOR
36
33
0.714 Vp-p
Red D/A output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75 Ohm lines.
IOG
35
32
1 V p-p
Green D/A output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75 Ohm lines.
Sync pulses may be added to the Green D/A output.
IOB
32
29
0.714 Vp-p
Blue D/A output. The current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75 Ohm lines.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC3003KRC30 | 功能描述:數(shù)字化視頻/模擬轉(zhuǎn)換器集成電路 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:3 輸出類型:Current 轉(zhuǎn)換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray |
| TMC3003KRC30T | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TMC3003KRC50 | 功能描述:數(shù)字化視頻/模擬轉(zhuǎn)換器集成電路 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:3 輸出類型:Current 轉(zhuǎn)換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray |
| TMC3003KRC50T | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TMC3003KRC80 | 功能描述:數(shù)字化視頻/模擬轉(zhuǎn)換器集成電路 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:3 輸出類型:Current 轉(zhuǎn)換速率:180 MSPs 分辨率:10 bit 接口類型:Parallel 電壓參考:Internal or External 積分非線性:- 2.5 LSB, 1.5 LSB 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:HTQFP 封裝:Tray |
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