參數(shù)資料
型號(hào)： TMDS442PNPRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝： PLASTIC, TQFP-128
文件頁(yè)數(shù)： 17/45頁(yè)
文件大?。?/td> 1977K
代理商： TMDS442PNPRG4
www.ti.com
APPLICATION INFORMATION
I
2C Interface Notes
Start
Condition
Stop
Condition
SDA
SCL
S
P
General I
2C Protocol
SLLS757A – AUGUST 2006 – REVISED MARCH 2007
The I2C interface is used to access the internal registers of the TMDS442. I2C is a two-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL.
A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus
under control of the master device. The TMDS442 works as a slave and supports the standard mode transfer
(100 kbps) and fast mode transfer (400 kbps) as defined in the I2C-Bus Specification. The TMDS442 has been
tested to be fully functional with the high-speed mode (3.4 Mbps) but is not ensured at this time.
The basic I2C start and stop access cycles are shown in Figure 23. The basic access cycle consists of the
following:
A start condition
A slave address cycle
Any number of data cycles
A stop condition
Figure 23. I2C Start and Stop Conditions
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 23. All I2C-compatible devices should
recognize a start condition.
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 23). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 25) by pulling the SDA line low during
the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from
the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
an acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (see Figure 26).
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 23). This releases the bus and stops the communication link
with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
24
Copyright 2006–2007, Texas Instruments Incorporated
Product Folder Link(s): TMDS442
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