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參數(shù)資料
| 型號： | TMDS461PZT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 12/43頁 |
| 文件大?。?/td> | 3111K |
| 代理商： | TMDS461PZT |
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DESCRIPTION (CONTINUED)
SLLS915 – JANUARY 2009 ............................................................................................................................................................................................... www.ti.com
When any input port is selected, the integrated terminations (50-
termination resistors pulled up to VCC) are
switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is
enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled,
and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are
switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry
provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations
on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state.
The TMDS461 is designed to be controlled via a local I2C interface or GPIO interface based on the status of the
I2C_SEL pin. The local I2C interface in TMDS461 is a slave-only I2C interface. (See the I2C INTERFACE
NOTES section.)
I2C Mode: When the I2C_SEL pin is set high, the device is in I2C mode. Refer to Table 7 to Table 13 for I2C
register description. With local I2C, the interface port status can be read and the advanced configurations of the
device such as TMDS output edge rate control, DDC I2C buffer output-voltage-select (OVS) settings (See the
DDC I2C Function Description for detailed description on DDC I2C buffer description and OVS description),
device power management, TMDS clock-detect feature, Automatic Port Selection and TMDS input-port
selection can be set. In I2C mode when any system level change such as change in 5V_PWR on the source
side, a change in the selected port, or a change in the selected port's valid clock detect is detected, TMDS461
can issue an Interrupt Request via IRQ pin (refer IRQ Section ). A micro-controller connected to TMDS461 can
read I2C register address 0X01, (See Table 7) to obtain the current status of 5V_PWR, the selected port, and
clock-detect status. Once the micro-controller has read I2C register 0x01, the IRQ pin returns to low.
GPIO mode: When the I2C_SEL pin is set low, the device is in GPIO control mode. The port selection is
controlled with source selectors, S1 and S2. The power-saving mode is controlled through the LP pin. In GPIO
mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set. The DDC I2C
buffer OVS setting can be changed through OVS GPIO pin, see Table 2. In GPIO mode, IRQ pin reflects the
status of the selected port's clock detect. If a valid clock is detected by the clock detect circuit, IRQ goes high. If
no valid clock is detected, IRQ is driven low.
Following are some of the key features (advantages) that TMDS461 provides to the overall sink-side system
(HDTV).
4:1 switch that supports TMDS data rates up to 3 Gbps on all four input ports.
ESD: Built-in support for high ESD protection (up to 10 kV on the TMDS and DDC I2C pins ). The HDMI
source-side pins on the TMDS461 are connected via the HDMI/DVI exterior connectors and cable to the
HDMI/DVI sources (e.g., DVD player). In TV applications, it can be expected that the source side may be
subjected to higher ESD stresses compared to the sink side that is connected internally to the HDMI receiver.
Adaptive equalization: The built-in analog adaptive equalization support compensates for intersymbol
interference [ISI] loss of up to 20 dB, which represents a typical 20-m HDMI/DVI cable at 3 Gbps. Analog
Adaptive equalization adjusts the equalization gain automatically, based on the cable length and the
incoming TMDS data rate.
TMDS clock-detect circuitry: This feature provides an automatic power-management feature and also ensures
that the TMDS output port is turned on only if there is a valid TMDS input signal. TMDS clock-detect feature
can be by-passed in I2C Mode, (See Table 9 ). It is recommended to enable TMDS clock-detect circuitry
during normal operation. However, for HDMI compliance testing (TMDS Termination Voltage Test), the clock
detect feature should be disabled by using the I2C mode control. To comply with the TMDS Termination
Voltage Test in the GPIO mode (default TMDS clock-detect circuitry enabled), a valid TMDS clock will need to
be provided. With the clock present, the internal terminations are present providing the correct termination
voltage.
DDC I2C buffer: This feature provides isolation on the source side and sink side DDC I2C capacitance, thus
helping the sink system to pass system-level compliance.
Robust TMDS receive stage: This feature ensures that the TMDS461 can work with TMDS input signals
which have common-mode voltage levels that can be either compliant or non-compliant with HDMI/DVI
specifications
VSadj: This feature adjusts the TMDS output swing and can help the sink system to tune the output TMDS
swing of the TMDS461 (if needed) based on the system requirements.
GPIO or local I2C interface to control the device features
2
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s) :TMDS461
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