參數(shù)資料
型號(hào): TMP320F2810GHHMEP
廠商: Texas Instruments, Inc.
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 81/103頁(yè)
文件大?。?/td> 1341K
代理商: TMP320F2810GHHMEP
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
APRIL 2001
REVISED SEPTEMBER 2001
81
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
serial communications interface (SCI) module (continued)
Figure 19 shows the SCI module block diagram.
TX FIFO _0
TX FIFO _1
TX FIFO _15
LSPCLK
WUT
Frame Format and Mode
Even/Odd
SCICCR.6 SCICCR.5
Enable
Parity
SCI RX Interrupt select logic
BRKDT
SCIRXST.5
RXRDY
SCIRXST.6
SCICTL1.3
1
8
SCICTL2.1
RX/BK INT ENA
SCIRXD
SCIRXST.1
TXENA
SCI TX Interrupt select logic
TX EMPTY
SCICTL2.6
TXRDY
SCICTL2.7
SCICTL2.0
TX INT ENA
SCITXD
RXENA
SCIRXD
RXWAKE
SCICTL1.6
RX ERR INT ENA
TXWAKE
SCITXD
SCITXBUF.7–0
SCIHBAUD. 15 – 8
Baud Rate
MSbyte
Register
SCILBAUD. 7 – 0
Transmitter
Data
Buffer Register
8
Baud Rate
LSbyte
Register
RXSHF
Register
TXSHF
Register
8
TX FIFO registers
TX FIFO Interrupt
TX Interrupt
Logic
TXINT
SCIFFTX.14
RX FIFO _15
RX FIFO_1
RX FIFO _0
SCIRXBUF.7–0
Receive Data
Buffer register
SCIRXBUF.7
0
8
RX FIFO registers
SCICTL1.0
RX Interrupt
Logic
RXINT
RX FIFO Interrupt
SCIFFRX.15
RXFFOVF
RX Error
SCIRXST.7
PE
FE OE
RX Error
SCIRXST.4 – 2
To CPU
To CPU
AutoBaud Detect logic
SCICTL1.1
SCIFFENA
Figure 19. Serial Communications Interface (SCI) Module Block Diagram
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