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參數(shù)資料
| 型號： | TMP320F2810PGFAEP |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 59/103頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | TMP320F2810PGFAEP |
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
59
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
32-bit CPU-Timers 0/1/2 (continued)
Table 48. TIMERxTCR Register Bit Definitions
BIT
NAME
R/W
RESET
DESCRIPTION
15
TIF
R/W=1
0
Timer Interrupt Flag. This flag gets set when the timer decrements to zero. This bit can be
cleared by software writing a 1, but it can only be set by the timer reaching zero. Writing a 1
to this bit will clear it, writing a zero has no effect.
14
TIE
R/W
0
Timer Interrupt Enable. If the timer decrements to zero, and this bit is set, the timer will assert
its interrupt request.
13:12
Reserved
R
0
Reserved
11
FREE
R/W
0
Timer Emulation Modes: These bits are special emulation bits that determine the state of
the timer when a breakpoint is encountered in the high-level language debugger. If the
FREE bit is set to 1, then, upon a software breakpoint, the timer continues to run (that is,
free runs). In this case, SOFT is a
don’t care
. But if FREE is 0, then SOFT takes effect. In
this case, if SOFT = 0, the timer halts the next time the TIMH:TIM decrements. If the SOFT
bit is 1, then the timer halts when the TIMH:TIM has decremented to zero.
FREE
SOFT
Timer Emulation Mode
10
SOFT
R/W
0
0
0
1
1
0
1
0
1
Stop after the next decrement of the TIMH:TIM (hard stop)
Stop after the TIMH:TIM decrements to 0 (soft stop)
Free run
Free run
Note:
That in the SOFT STOP mode, the timer will generate an interrupt before
shutting down (since reaching 0 is the interrupt causing condition).
9:6
Reserved
R/W
0
Reserved
5
TRB
W/R=0
0
Timer Reload bit. When you write a 1 to TRB, the TIMH:TIM is loaded with the value in the
PRDH:PRD, and the prescaler counter (PSCH:PSC) is loaded with the value in the timer
divide-down register (TDDRH:TDDR). The TRB bit is always read as zero.
4
TSS
R/W
0
Timer stop status bit. TSS is a 1-bit flag that stops or starts the timer. To stop the timer, set
TSS to 1. To start or restart the timer, set TSS to 0. At reset, TSS is cleared to 0 and the timer
immediately starts.
3:0
Reserved
R/W
0
Reserved
x = 0, 1, or 2
P
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