參數(shù)資料
型號: TMP90CH45
廠商: Toshiba Corporation
元件分類: 通用總線功能
英文描述: High Speed Advanced CMOS 8-bit Microcontroller,Integrating 8-Bit A/D Converter,RAM,ROM,General Serial Interface,Multifuction Timer/Event Counter,Programmable Chip Selector Features(高速、先進的 CMOS 8位微控制器(芯片集成了8位A/D轉(zhuǎn)換器,ROM,RAM,通用串行接口,多功能定時器/事件計數(shù)器,可編程芯片選擇器))
中文描述: 采用先進的CMOS高速8位微控制器,集成8位A / D轉(zhuǎn)換器,內(nèi)存,光盤,通用串行接口,Multifuction定時器/事件計數(shù)器,可編程芯片選擇功能(高速,先進的的CMOS 8位微控制器(芯片集成了8位的A / D轉(zhuǎn)換器,ROM和RAM內(nèi)存,通用串行接口,多功能定時器/事件計數(shù)器,可編程芯片選擇器))
文件頁數(shù): 5/14頁
文件大?。?/td> 385K
代理商: TMP90CH45
TOSHIBA CORPORATION
5/14
TMP90CH45
2.2 Pin Names and Functions
The names of input/output pins and their functions are summarized in Table 2.2.
Table 2.2 Pin Names and Functions (1/2)
Pin Name
No. of pins
I/O or tristate
Function
AD0 ~ AD7
Tristate
Address/data bus: 8-bit time sharing bus which transmits address (lower 8 bits) and data
A8 ~ A15
8
Output
Address bus: The upper 8 bits address bus
P20 ~ P26
/A16 ~ A20
/A21 ~ A22
/ROMCS,
RAMCS
IOCS
7
(5)
(2)
(3)
Output
/Output
/Output
Port 20 ~ 26: 7-bit output port
Addresses 16 ~ 20: Address bus which is used to expand the program and data areas.
Addresses 21 and 22: Address bus which is used to extend the program and data area (inverted output)
/Output
Programmable chip select
P27
8
Input
Port 27: 1-bit input port
/WAIT
Input
Wait: Input pin for connecting a memory or peripheral LSI with delayed access time.
P30 ~ P37/
8
I/O
Port 3: 8-bit I/O port which allows I/O selection on bit basis (with programmable pull-up resistor).
/RxD
(1)
Input
Receiver of serial data
/SCLK
(1)
/I/O
Serial clock
/TxD
(1)
/Output
Transmitter of serial data
P40 ~ P47
8
I/O
Port 4: 8-bit I/O port which allows I/O selection on bit basis (with programmable pull-up resistor).
/TO1, 3, 4, 5
(4)
/Output
Timer outputs 1, 3, 4, and 5: Output ports for timer 0, or timer 1, timer 2, timer 3 and timer 4 (2 lines).
/TI0, 2, 4, 5
(4)
/Input
Timer inputs 0, 2, 4, and 5: Input ports for timer 0, or timer 1, timer 2 and timer 4 (2 lines).
/INT0
(1)
/Input
Interrupt request terminal 0: Interrupt request pin 0: Level/rise edge programmable interrupt request pin.
/INT1
(1)
/Input
Interrupt request terminal 1: Interrupt request pin 1: Rise/fall edge programmable interrupt request pin
/INT2
(1)
/Input
Interrupt request terminal 2: Interrupt request pin 2: Rise edge interrupt request pin.
P50 ~ P53
/AN0 ~ AN3
4
Input
Port 5: 4-bit output ports.
Analog input: 4 analog inputs to A/D converter.
P60 ~ P63
/M00 ~ M03
4
I/O
/Output
Port 6: 4 bit I/O port which allows I/O selection on bit basis.
Stepping motor control port 0 or pattern generation port 0
P70 ~ P73
/M10 ~ M13
4
I/O
Output
Port 7: 4 bit I/O port which allows I/O selection on bit basis.
Stepping motor control port 0 or pattern generation port 1
RD
1
Output
Read: Strobe signal output for reading external memory
WR
1
Output
Write: Strobe signal output for writing an external memory
ALE
1
Output
Address latch enable
CLK
1
Output
Clock output: Generates clock pulse at 1/4 frequency of clock oscillation.
It is pulled up internally during resetting.
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