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參數(shù)資料
| 型號： | TMP90PH02 |
| 廠商： | Toshiba Corporation |
| 英文描述： | A System Evaluation LSI With 8-Bit CPU,One-Time PROM(16384 x 8-Bit),RAM(512 x 8-Bit)(系統(tǒng)評估大規(guī)模集成電路（集成8位CPU，一次可編程ROM(16384 x 8位),RAM(512 x 8位)) |
| 中文描述： | 一個(gè)系統(tǒng)評價(jià)芯片與8位CPU，一次性可編程（16384 × 8位），內(nèi)存（512 × 8位）（系統(tǒng)評估大規(guī)模集成電路（集成8位的CPU，一次可編程ROM更新（16384 x 8位），內(nèi)存（512 × 8位）） |
| 文件頁數(shù)： | 11/14頁 |
| 文件大小： | 453K |
| 代理商： | TMP90PH02 |
TOSHIBA CORPORATION
11/14
TMP90PH02
4.4 Zero - Cross Characteristics
V
CC
= 5V
±
10% TA = -40 ~ 85
°
C (1 ~ 10MHz)
TA = -20 ~ 70
°
C (1 ~ 16MHz)
Symbol
Parameter
Condition
Min
Max
Unit
V
ZX
A
ZX
F
ZX
Zero-cross detection input
AC coupling C = 0.1
μ
F
50/60Hz sine wave
1
1.8
VAC p - p
Zero-cross accuracy
–
135
mV
Zero-cross detection input frequency
–
0.04
1
kHz
4.5 Serial Channel Timing - I/O Interface Mode
V
CC
= 5V
±
10% TA = -40 ~ 85
°
C (1 ~ 10MHz)
CL = 50pF TA = -20 ~ 70
°
C (1 ~ 16MHz)
Symbol
Parameter
Variable
10MHz Clock
16MHz Clock
Unit
Min
Max
Min
Max
Min
Max
t
SCY
t
OSS
t
OHS
t
HSR
t
SRD
Serial Port Clock Cycle Time
8x
–
640
–
500
–
ns
Output Data Setup SCLK Rising Edge
6x - 150
–
330
–
225
–
ns
Output Data Hold After SCLK Rising Edge
2x - 80
–
40
–
45
–
ns
Input Data Hold After SCLK Rising Edge
0
–
0
–
0
–
ns
SCLK Rising Edge to Input DATA Valid
–
6x - 150
–
330
–
225
ns
4.6 8-bit Event Counter
V
CC
= 5V
±
10% TA = -40 ~ 85
°
C (1 ~ 10MHz)
CL = 50pF TA = -20 ~ 70
°
C (1 ~ 16MHz)
Symbol
Parameter
Variable
10MHz Clock
16MHz Clock
Unit
Min
Max
Min
Max
Min
Max
t
VCK
t
VCKL
t
VCKH
TI2 clock cycle
8x + 100
–
740
–
600
–
ns
TI2 Low clock pulse width
4x + 40
–
360
–
290
–
ns
TI2 High clock pulse width
4x + 40
–
360
–
290
–
ns
4.7 Interrupt Operation
V
CC
= 5V
±
10% TA = -40 ~ 85
°
C (1 ~ 10MHz)
CL = 50pF TA = -20 ~ 70
°
C (1 ~ 16MHz)
Symbol
Parameter
Variable
10MHz Clock
16MHz Clock
Unit
Min
Max
Min
Max
Min
Max
t
INTAL
NMI, INT0 Low level pulse width
4x
–
320
–
250
–
ns
t
INTAH
NMI, INT0 High level pulse width
4x
–
320
–
250
–
ns
t
INTBL
INT1, INT2 Low level pulse width
8x + 100
–
740
–
600
–
ns
t
INTBH
INT1, INT2 High level pulse width
8x + 100
–
740
–
600
–
ns
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