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參數(shù)資料
| 型號(hào)： | TMS27C010A-15 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Programmable Read-Only Memory(128K×8結(jié)構(gòu),可擦可編程只讀存儲(chǔ)器) |
| 中文描述： | 可編程只讀存儲(chǔ)器（128K的× 8結(jié)構(gòu)，可擦可編程只讀存儲(chǔ)器） |
| 文件頁數(shù)： | 4/13頁 |
| 文件大小： | 269K |
| 代理商： | TMS27C010A-15 |
TMS27C010A 1048576-BIT UV ERASABLE PROGRAMMABLE
TMS27PC010A 1048576-BIT PROGRAMMABLE
READ-ONLY MEMORY
SMLS110B – NOVEMBER 1990 – REVISED JUNE 1995
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
operation
The seven modes of operation are listed in the following table. The read mode requires a single 5-V supply. All
inputs are TTL level except for V
PP
during programming (13 V for SNAP! Pulse), and 12 V on A9 for signature
mode.
FUNCTION
MODE
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE MODE
E
VIL
VIL
X
VIL
VIH
X
VIH
X
VIL
VIH
VIL
VPP
VCC
X
VIL
VIL
VIH
VPP
VCC
X
VIH
X
VIL
VIL
X
G
PGM
X
X
VPP
VCC
A9
VCC
VCC
X
VCC
VCC
X
VCC
VCC
X
VPP
VCC
X
VCC
VCC
VH
VIL
VH
VIH
A0
X
X
X
X
X
X
DQ0 DQ7
DQ0–DQ7
Data Out
Hi Z
Hi-Z
Hi Z
Hi-Z
Data In
Data Out
Hi Z
Hi-Z
CODE
MFG
97
DEVICE
D6
X can be VIL or VIH.
VH = 12 V
±
0.5 V.
read/output disable
When the outputs of two or more TMS27C010As or TMS27PC010As are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All other
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C010A and TMS27PC010A is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry standard TTL or MOS logic devices. The input/output layout approach controls
latchup without compromising performance or packing density.
power down
Active I
CC
supply current can be reduced from 30 mA to 500
μ
A by applying a high TTL input on E and to
100
μ
A by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure (TMS27C010A)
Before programming, the TMS27C010A EPROM is erased by exposing the chip through the transparent lid to
a high intensity ultraviolet light (wavelength 2537 ). The recommended minimum exposure dose (UV intensity
×
exposure time) is 15-W
s/cm
2
. A typical 12-mW/cm
2
, filterless UV lamp erases the device in 21 minutes. The
lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state.
It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using
the TMS27C010A, the window should be covered with an opaque label. After erasure (all bits in logic high state),
logic lows are programmed into the desired locations. A programmed low can be erased only by ultraviolet light.
initializing (TMS27PC010A)
The one-time programmable TMS27PC010A PROM is provided with all bits in the logic high state, then logic
lows are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
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