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| 型號： | TMS27PC020-25FML |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | READ-ONLY MEMORIES |
| 中文描述： | 只讀存儲器 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 206K |
| 代理商： | TMS27PC020-25FML |
TMS27C020 262144 BY 8-BIT UV ERASABLE
TMS27PC020 262144 BY 8-BIT
PROGRAMMABLE READ-ONLY MEMORIES
SMLS020C – NOVEMBER 1990 – REVISED SEPTEMBER 1997
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
CI
CO
Capacitance measurements are made on sample basis only.
All typical values are at TA = 25
°
C and nominal voltages.
Input capacitance
VI = 0 V,
VO = 0 V,
f = 1 MHz
4
8
pF
Output capacitance
f = 1 MHz
6
10
pF
switching characteristics over full ranges of recommended operating conditions (see Notes 3
and 4)
TEST
’27C020-10
’
27PC020-10
’27C020-12
’
27PC020-12
’27C020-15
’27PC020-15
27C020-20
27PC020-20
’27C020-25
’27PC020-25
PARAMETER
CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
ta(A)
Access
from address
time
100
120
150
200
250
ns
ta(E)
Access
from chip en-
able
time
100
120
150
200
250
ns
ten(G)
Output enable
time from G
CL = 100 pF,
1 Series 74
TTL load,
Input tr
≤
20 ns,
Input tf
≤
20 ns
55
55
75
75
100
ns
tdis
Output disable
time from G or
E,
whichever
occurs first
Output data
valid time after
change of ad-
dress, E, or G,
whichever oc-
curs first§
0
50
0
50
0
60
0
60
0
80
ns
tv(A)
0
0
0
0
0
ns
§Value calculated from 0.5-V delta to measured output level. This parameter is sampled and not 100% tested.
NOTES:
3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high
and 0.8 V for logic low. (See Figure 2).
4. Common test conditions apply for tdis except during programming.
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