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參數(shù)資料
| 型號(hào)： | TMS320AV120 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MPEG Audio Decoder(MPEG音頻譯碼器) |
| 中文描述： | MPEG音頻解碼器（的MPEG音頻譯碼器） |
| 文件頁(yè)數(shù)： | 6/17頁(yè) |
| 文件大?。?/td> | 380K |
| 代理商： | TMS320AV120 |
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TMS320AV120
MPEG AUDIO DECODER
SCSS014A – MARCH 1994 – REVISED JANUARY 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
input interface
The TMS320AV120 accepts MPEG audio streams; MPEG system and packet streams can not be decoded.
Compressed data and synchronization information is input serially on SIN, using ICLK, SREQ, and SMODE.
If SREQ is low, data set up on SIN is latched on the rising edge of ICLK. The device accepts one additional bit
of data after SREQ goes high. Data input thereafter may corrupt the bit received previously. SREQ goes high
if RESET goes active (low) or the input buffer is full. A 512-byte internal buffer is used to buffer the compressed
data to absorb minor input bit-rate variations. SREQ does not go high (inactive) as long as the input data rate
does not exceed 448 kbit/s. Figure 2 and Figure 3 show constant-bit-rate and burst-data input timing.
ERR_IN is an input used to signal to the decoder that the data coming in may not be correct. The frame
containing the data bit(s) that may be invalid (corresponding to ERR_IN high) are muted if the data is from the
beginning of the frame through the scale factors. The ’AV120 is capable of responding to at least one error per
every 512 bytes of compressed data. This prevents errors in the data stream from damaging speakers. If not
used, ERR_IN should be tied low. Figure 2 shows the proper timing for the ERR_IN signal.
The SMODE input signals the presence of timing information. When SMODE is low, the data on the SIN terminal
is interpreted as compressed-audio data. When SMODE transitions high, the next 34 bits of the serial data is
interpreted as either a PTS if bit 33 is a zero or an SCR if bit 33 is a one. Bit 33 should be on SIN during the same
ICLK cycle that SMODE transitions high. SMODE timing is shown in Figure 3.
An additional input, HSYNC, can be used in systems where hardware frame synchronization is available, such
as the proposed Eureka DAB systems. When HSYNC transitions high, the next 12 bits are assumed to be an
audio-frame-synchronization word. If not used, HSYNC should be tied low. HSYNC input timing is shown in
Figure 4.
The ’AV120 has an audio-bypass feature that allows 16-bit PCM data to be loaded into the device and passed
through to the PCMDATA output. To use the audio-bypass feature, BYPASS must be set high. Changing to or
from bypass mode requires a reset.
1/fclock
tsu1
tsu2
tsu2
th1
tsu3
th2
Data
Data
SIN
ERR_IN
SREQ
ICLK
ICLK must be at the encoded stream bit rate.
Figure 2. Constant-Bit-Rate Input Timing
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