參數(shù)資料
型號(hào): TMS320C6414TBZLZ8
廠商: Texas Instruments
文件頁(yè)數(shù): 91/146頁(yè)
文件大?。?/td> 0K
描述: IC FIXED-POINT DSP 532-FCBGA
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C6414T/15T/16T
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP,PCI,UTOPIA
時(shí)鐘速率: 850MHz
非易失內(nèi)存: 外部
芯片上RAM: 1.03MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 532-BFBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 532-FCBGA(23x23)
包裝: 托盤
配用: TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
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TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
49
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions (Continued)
SIGNAL
TYPE
IPD/
DESCRIPTION
NAME
NO.
TYPE
IPD/
IPU
DESCRIPTION
EMIFB (16-bit) CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY||k
BCE3
A13
O/Z
IPU
EMIFB memory space enables
BCE2
C12
O/Z
IPU
EMIFB memory space enables
Enabled by bits 26 through 31 of the word address
BCE1
B12
O/Z
IPU
Enabled by bits 26 through 31 of the word address
Only one pin is asserted during any external data access
BCE0
A12
O/Z
IPU
Only one pin is asserted during any external data access
BBE1
D13
O/Z
IPU
EMIFB byte-enable control
Decoded from the low-order address bits. The number of address bits or byte enables
used depends on the width of external memory.
BBE0
C13
O/Z
IPU
used depends on the width of external memory.
Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
BPDT
E12
O/Z
IPU
EMIFB peripheral data transfer, allows direct transfer between external peripherals
EMIFB (16-BIT) BUS ARBITRATION||k
BHOLDA
E13
O
IPU
EMIFB hold-request-acknowledge to the host
BHOLD
B19
I
IPU
EMIFB hold request from the host
BBUSREQ
E14
O
IPU
EMIFB bus request output
EMIFB (16-BIT) ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL||k
BECLKIN
A11
I
IPD
EMIFB external input clock. The EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock)
is selected at reset via the pullup/pulldown resistors on the BEA[15:14] pins.
BECLKIN is the default for the EMIFB input clock.
BECLKOUT2
D11
O/Z
IPD
EMIFB output clock 2. Programmable to be EMIFB input clock (BECLKIN, CPU/4 clock, or
CPU/6 clock) frequency divided by 1, 2, or 4.
BECLKOUT1
D12
O/Z
IPD
EMIFB output clock 1 [at EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
BARE/
BSDCAS/
BSADS/BSRE
A10
O/Z
IPU
EMIFB asynchronous memory read-enable/SDRAM column-address strobe/programmable
synchronous interface-address strobe or read-enable
For programmable synchronous interface, the RENEN field in the CE Space Secondary
Control Register (CExSEC) selects between BSADS and BSRE:
If RENEN = 0, then the BSADS/BSRE signal functions as the BSADS signal.
If RENEN = 1, then the BSADS/BSRE signal functions as the BSRE signal.
BAOE/
BSDRAS/
BSOE
B11
O/Z
IPU
EMIFB asynchronous memory output-enable/SDRAM row-address strobe/programmable
synchronous interface output-enable
BAWE/BSDWE/
BSWE
C11
O/Z
IPU
EMIFB asynchronous memory write-enable/SDRAM write-enable/programmable synchro-
nous interface write-enable
BSOE3
E15
O/Z
IPU
EMIFB synchronous memory output enable for BCE3 (for glueless FIFO interface)
BARDY
E11
I
IPU
EMIFB asynchronous memory ready input
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
|| These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
kTo maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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