參數(shù)資料
型號： TMS320C6416TBZLZ1
廠商： Texas Instruments
文件頁數(shù)： 12/146頁
文件大?。?/td> 0K
描述： IC FIXED-POINT DSP 532-FCBGA
標準包裝： 60
系列： TMS320C6414T/15T/16T
類型： 定點
接口： 主機接口，McBSP，PCI，UTOPIA
時鐘速率： 1.0GHz
非易失內(nèi)存： 外部
芯片上RAM： 1.03MB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 532-BFBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 532-FCBGA（23x23）
包裝： 托盤
配用： 701891-ND - KIT STARTER DSP FOR C6416T
TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
109
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
HOST-PORT INTERFACE (HPI) TIMING
timing requirements for host-port interface cycles (see Figure 39 through Figure 46)
NO.
600
850
720
1G
UNIT
MIN
MAX
1
tsu(SELV-HSTBL)
Setup time, select signals§ valid before HSTROBE low
5
ns
2
th(HSTBL-SELV)
Hold time, select signals§ valid after HSTROBE low
2.4
ns
3
tw(HSTBL)
Pulse duration, HSTROBE low
4P
ns
4
tw(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses
4P
ns
10
tsu(SELV-HASL)
Setup time, select signals§ valid before HAS low
5
ns
11
th(HASL-SELV)
Hold time, select signals§ valid after HAS low
2
ns
12
tsu(HDV-HSTBH)
Setup time, host data valid before HSTROBE high
5
ns
13
th(HSTBH-HDV)
Hold time, host data valid after HSTROBE high
2.8
ns
14
th(HRDYL-HSTBL)
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
2
ns
18
tsu(HASL-HSTBL)
Setup time, HAS low before HSTROBE low
2
ns
19
th(HSTBL-HASL)
Hold time, HAS low after HSTROBE low
2.1
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
§ Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
Select the parameter value of 4P or 12.5 ns, whichever is greater.
switching characteristics over recommended operating conditions during host-port interface
cycles (see Figure 39 through Figure 46)
NO.
PARAMETER
600
850
720
1G
UNIT
MIN
MAX
6
td(HSTBL-HRDYH)
Delay time, HSTROBE low to HRDY high#
1.3
4P + 8
ns
7
td(HSTBL-HDLZ)
Delay time, HSTROBE low to HD low impedance for an HPI read
2
ns
8
td(HDV-HRDYL)
Delay time, HD valid to HRDY low
3
ns
9
toh(HSTBH-HDV)
Output hold time, HD valid after HSTROBE high
1.5
ns
15
td(HSTBH-HDHZ)
Delay time, HSTROBE high to HD high impedance
12
ns
16
td(HSTBL-HDV)
Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only)
4P + 8
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.
# This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16)
on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until
the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is
full.
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TMS320C6416TBZLZA6 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
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