參數(shù)資料
型號(hào)： TMS320F240PQQ
英文描述： 16-Bit Microcontroller
中文描述： 16位微控制器
文件頁(yè)數(shù)： 7/105頁(yè)
文件大?。?/td> 1481K
代理商： TMS320F240PQQ
TMS320C240, TMS320F240
DSP CONTROLLERS
SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions (Continued)
TERMINAL
NAME
TYPE
DESCRIPTION
NO.
EXTERNAL INTERFACE CONTROL SIGNALS (CONTINUED)
BR
5
O/Z
Bus request. BR is asserted during access of external global data memory space. BR can be
used to extend the data memory address space by up to 32K words. BR goes in the
high-impedance state during reset, power down, and when EMU1/OFF is active low.
WDDIS
50
I
Flash-programming voltage supply. If VCCP = 5 V, then WRITE/ERASE can be made to the
ENTIRE on-chip flash memory block—that is, for programming the flash. If VCCP = 0 V, then
WRITE/ERASE of the flash memory is not allowed, thereby protecting the entire memory block
from being overwritten. WDDIS also functions as a hardware watchdog disable. The watchdog
timer is disabled when VCCP/WDDIS = 5 V and bit 6 in WDCR is set to 1.
ADC INPUTS (UNSHARED)
ADCIN2
74
I
ADCIN3
75
I
ADCIN4
76
I
Analog inputs to the first ADC
ADCIN5
77
I
ADCIN6
78
I
ADCIN7
79
I
ADCIN10
89
I
ADCIN11
88
I
ADCIN12
83
I
Analog inputs to the second ADC
ADCIN13
82
I
ADCIN14
81
I
ADCIN15
80
I
BIT I/O AND SHARED FUNCTIONS PINS
ADCIN0/IOPA0
72
I/O
Bidirectional digital I/O.
Analog input to the first ADC.
ADCIN0/IOPA0 is configured as a digital input by all device resets.
ADCIN1/IOPA1
73
I/O
Bidirectional digital I/O.
Analog input to the first ADC.
ADCIN1/IOPA1 is configured as a digital input by all device resets.
ADCIN9/IOPA2
90
I/O
Bidirectional digital I/O.
Analog input to the second ADC.
ADCIN9/IOPA2 is configured as a digital input by all device resets.
ADCIN8/IOPA3
91
I/O
Bidirectional digital I/O.
Analog input to the second ADC.
ADCIN8/IOPA3 is configured as a digital input by all device resets.
PWM7/CMP7/IOPB0
100
I/O/Z
Bidirectional digital I/O. Simple compare/PWM 1 output. The state of PWM7/CMP7/IOPB0 is
determined by the simple compare/PWM and the simple action control register (SACTR). It
goes to the high-impedance state when unmasked PDPINT goes active low.
PWM7/CMP7/IOPB0 is configured as a digital input by all device resets.
PWM8/CMP8/IOPB1
101
I/O/Z
Bidirectional digital I/O. Simple compare/PWM 2 output. The state of PWM8/CMP8/IOPB1 is
determined by the simple compare/PWM and the SACTR. It goes to the high-impedance state
when unmasked PDPINT goes active low. PWM8/CMP8/IOPB1 is configured as a digital input
by all device resets.
PWM9/CMP9/IOPB2
102
I/O/Z
Bidirectional digital I/O. Simple compare/PWM 3 output. The state of PWM9/CMP9/IOPB2 is
determined by the simple compare/PWM and SACTR. It goes to the high-impedance state
when unmasked PDPINT goes active low. PWM9/CMP9/IOPB2 is configured as a digital input
by all device resets.
I = input, O = output, Z = high impedance
For the TMS320F240 devices, this pin is VCCP/WDDIS.
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