- 您現(xiàn)在的位置：買賣IC網 > PDF目錄385940 > TMS320F28044GGMQ (Texas Instruments, Inc.) Digital Signal Processor PDF資料下載
參數(shù)資料
| 型號： | TMS320F28044GGMQ |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processor |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 22/105頁 |
| 文件大?。?/td> | 768K |
| 代理商： | TMS320F28044GGMQ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁
www.ti.com
A
3.2
Brief Descriptions
3.2.1
C28x CPU
3.2.2
Memory Bus (Harvard Bus Architecture)
TMS320F28044
Digital Signal Processor
SPRS357A–AUGUST 2006–REVISED OCTOBER 2006
Table 3-2. Wait-states
AREA
WAIT-STATES
0-wait
0-wait
0-wait (writes)
2-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait
COMMENTS
Fixed
Fixed
M0 and M1 SARAMs
Peripheral Frame 0
Peripheral Frame 1
Fixed.
Peripheral Frame 2
Fixed
L0 & L1 SARAMs
Programmed via the Flash registers. 1-wait-state operation
is possible at a reduced CPU frequency. See Section
Section 3.2.5
for more information.
Programmed via the Flash registers. 0-wait-state operation
is possible at reduced CPU frequency. The CSM password
locations are hardwired for 16 wait-states. See Section
Section 3.2.5
for more information.
Fixed
Programmable,
1-wait minimum
OTP
Programmable,
0-wait minimum
Flash
Boot-ROM
1-wait
The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is a
very efficient C/C++ engine, hence enabling users to develop not only their system control software in a
high-level language, but also enables math algorithms to be developed using C/C++. The C28x is as
efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller
devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC
capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher
numerical resolution problems that would otherwise demand a more expensive floating-point processor
solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in
a device that is capable of servicing many asynchronous events with minimal latency. The C28x has an
8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to
execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead
hardware minimizes the latency for conditional discontinuities. Special store conditional operations further
improve performance.
As with many DSP type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed "Harvard Bus", enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
Highest:
Data Writes
Program Writes
Data Reads
Program Reads
Fetches
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
Lowest:
Functional Overview
22
Submit Documentation Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| TMS320F28044GGMS | Digital Signal Processor |
| TMS320F28044PZQ | Digital Signal Processor |
| TMS320LC545 | Digital Signal Processors(20/25ns指令周期， 高性能，大并行度，特殊指令集可有效實現(xiàn)多種復雜算法及應用的DSP) |
| TMS320LC546 | Digital Signal Processors(20/25ns指令周期， 高性能，大并行度，特殊指令集可有效實現(xiàn)多種復雜算法及應用的DSP) |
| TMS320LC57S | Digital Signal Processors(35/50ns指令周期，并行邏輯單元，可編程PLL，全雙工同步串行口的DSP) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320F28044PZA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 32-Bit DSC w/ 128KB Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320F28044PZS | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 32-Bit DSC w/ 128KB Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320F28045PZA | 制造商:Texas Instruments 功能描述:- Trays |
| TMS320F28045PZS | 制造商:Texas Instruments 功能描述:- Trays |
| TMS320F28050PNQ | 制造商:Texas Instruments 功能描述:GIZMO |
發(fā)布緊急采購，3分鐘左右您將得到回復。