參數(shù)資料
型號: TMS320F2809_07
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors
中文描述: 數(shù)字信號處理器
文件頁數(shù): 49/140頁
文件大?。?/td> 1108K
代理商: TMS320F2809_07
www.ti.com
3.6.1
OSC and PLL Block
X1
XCLKIN
(3.3-V clock input)
On chip
oscillator
X2
xor
PLLSTS[OSCOFF]
OSCCLK
PLL
VCOCLK
4-bit PLL Select (PLLCR)
OSCCLK or
VCOCLK
CLKIN
OSCCLK
0
PLLSTS[PLLOFF]
n
n
0
/2
PLLSTS[CLKINDIV]
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs
SPRS230J–OCTOBER 2003–REVISED SEPTEMBER 2007
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in
Table 3-15
.
Table 3-15. PLL, Clocking, Watchdog, and Low-Power Mode Registers
(1)
NAME
ADDRESS
0x7010
0x7011
0x7012 - 0x7019
0x701A
0x701B
0x701C
0x701D
0x701E
0x701F - 0x7020
0x7021
0x7022
0x7023
0x7024
0x7025
0x7026 - 0x7028
0x7029
0x702A - 0x702F
SIZE (x16)
1
1
8
1
1
1
1
1
1
1
1
1
1
1
3
1
6
DESCRIPTION
XCLK
PLLSTS
reserved
HISPCP
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
reserved
PLLCR
SCSR
WDCNTR
reserved
WDKEY
reserved
WDCR
reserved
XCLKOUT Pin Control, X1 and XCLKIN Status Register
PLL Status Register
High-Speed Peripheral Clock Prescaler Register (for HSPCLK)
Low-Speed Peripheral Clock Prescaler Register (for LSPCLK)
Peripheral Clock Control Register 0
Peripheral Clock Control Register 1
Low Power Mode Control Register 0
PLL Control Register
System Control and Status Register
Watchdog Counter Register
Watchdog Reset Key Register
Watchdog Control Register
(1)
All of the registers in this table are EALLOW protected.
Figure 3-10
shows the OSC and PLL block on the 280x.
Figure 3-10. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the 280x devices using the X1
and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the
following configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed V
DDIO
.
2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left
unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed V
DD
.
The three possible input-clock configurations are shown in
Figure 3-11
through
Figure 3-13
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Functional Overview
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