參數(shù)資料
型號： TMS320F28335_1
廠商： Texas Instruments, Inc.
英文描述： Variable Capacitance Diode for TV Tuner VHF Tuning; Ratings VR (V): 32; Characteristics n: 12.0 min; Characteristics rs (ohm) max: 0.85; Characteristics C (pF) max: C2 = 32.2 to 37.5 C25 = 2.57 to 3.0; Characteristics CVR/CVR: 2/25; Cl: 2.777; Package: UFP
中文描述： 數(shù)字信號控制器（DSC）
文件頁數(shù)： 135/166頁
文件大?。?/td> 1889K
代理商： TMS320F28335_1
www.ti.com
A
Data Valid
22
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
21
12
18
17
14
13
SPISTE
(A)
6.10.7 External Interface (XINTF) Timing
TMS320F28335, TMS320F28334, TMS320F28332
Digital Signal Controllers (DSCs)
SPRS439B–JUNE 2007–REVISED OCTOBER 2007
Table 6-36. SPI Slave Mode External Timing (Clock Phase = 1) (continued)
NO.
MIN
0.75t
c(SPC)S
MAX
UNIT
ns
t
v(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK low (clock polarity =
1)
21
t
su(SIMO-SPCH)S
t
su(SIMO-SPCL)S
t
v(SPCH-SIMO)S
35
35
ns
ns
ns
22
0.5t
c(SPC)S-10
t
v(SPCL-SIMO)S
0.5t
c(SPC)S-10
ns
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5t
c(SPC)
before the valid SPI clock edge and
remain low for at least 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 6-21. SPI Slave Mode External Timing (Clock Phase = 1)
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the
Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF
zone.
Table 6-37
shows the relationship between the parameters configured in the XTIMING register and
the duration of the pulse in terms of XTIMCLK cycles.
Table 6-37. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DESCRIPTION
DURATION (ns)
(1)(2)
X2TIMING = 0
XRDLEAD
×
t
c(XTIM)
(XRDACTIVE + WS + 1)
×
t
c(XTIM)
XRDTRAIL
×
t
c(XTIM)
X2TIMING = 1
(XRDLEAD
×
2)
×
t
c(XTIM)
(XRDACTIVE
×
2 + WS + 1)
×
t
c(XTIM)
(XRDTRAIL
×
2)
×
t
c(XTIM)
LR
AR
TR
Lead period, read access
Active period, read access
Trail period, read access
(1)
(2)
t
– Cycle time, XTIMCLK
WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
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Electrical Specifications
135
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