參數(shù)資料
型號(hào): TMS320LC541-66
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processor
中文描述: 數(shù)字信號(hào)處理器
文件頁數(shù): 96/111頁
文件大?。?/td> 1426K
代理商: TMS320LC541-66
TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
96
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
buffered serial port transmit timing of internal frame and internal clock
switching characteristics over recommended operating conditions for buffered serial port
transmit of internal frame and internal clock [H = 0.5tc(CO)] (see Figure 37)
PARAMETER
’C54x-40
’LC54x-40
’LC54x-50
’54x-66
UNIT
MIN
2H
MAX
62H
MIN
20
MAX
62H
tc(SCK)
Cycle time, serial port clock, internal clock
ns
td(BFSX)
Delay time, BFSX after BCLKX rising edge
(see Notes 3 and 4)
10
10
ns
td(BDX)
tdis(BDX)
tdis(BDX)pcm
ten(BDX)pcm
th(BDX)
tf(SCK)
tr(SCK)
tw(SCK)
NOTES:
Delay time, BDX valid after BCLKX rising edge
8
8
ns
Disable time, BDX after BCLKX rising edge
0
5
0
5
ns
Disable time, PCM mode, BDX after BCLKX rising edge
5
5
ns
Enable time, PCM mode, BDX after BCLKX rising edge
7
7
ns
Hold time, BDX valid after BCLKX rising edge
0
0
ns
Fall time, serial port clock
4
4
ns
Rise time, serial port clock
4
4
ns
Pulse duration, serial port clock low/high
H–4
6
ns
3. Internal clock with external BFSX and vice versa are also allowable. However, BFSX timings to BCLKX always are defined
depending on the source of BFSX, and BCLKX timings always are dependent upon the source of BCLKX.
4. Timings for BCLKX and BFSX are given with polarity bits (BCLKP and BFSP) set to 0.
8/10/12/16
2
1
BDX
BFSX
BCLKX
t
c(SCK)
t
d(BFSX)
t
d(BFSX)
t
dis(BDX)
t
w(SCK)
t
h(BDX)
t
d(BDX)
t
w(SCK)
tr(SCK)
tf(SCK)
Figure 37. Buffered Serial Port Transmit Timing of Internal Clocks and Internal Frames
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