參數(shù)資料
型號: TMS320LC542-50
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processor
中文描述: 數(shù)字信號處理器
文件頁數(shù): 30/111頁
文件大?。?/td> 1426K
代理商: TMS320LC542-50
TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039C – FEBRUARY 1996 – REVISED DECEMBER 1999
30
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
serial ports (continued)
When auto-buffering capability is disabled (standard mode), serial port transfers are performed under software
control through interrupts. In this mode, the ABU is transparent and the word-based interrupts (WXINT and
WRINT) provided by the serial port are sent to the CPU as transmit interrupt (XINT) and receive interrupt
(RINT). When auto buffering is enabled, word transfers are done directly between the serial port and the ’54x
internal memory using ABU-embedded address generators.
The ABU has its own set of circular-addressing registers with corresponding address-generation units. Memory
for the buffers resides in 2K words of the ’54x internal memory. The length and starting addresses of the buffers
are user-programmable. A buffer-empty/buffer-full interrupt can be posted to the CPU. Buffering is easily halted
by an auto-disabling capability. Auto-buffering capability can be enabled separately for transmit and receive
sections. When auto buffering is disabled, operation is similar to that of the general-purpose serial port.
The BSP allows transfer of 8-, 10-, 12-, or 16-bit data packets. In burst mode, data packets are directed by a
frame synchronization pulse for every packet. In continuous mode, the frame synchronization pulse occurs
when the data transmission is initiated and no further pulses occur. The frame and clock strobes are frequency-
and polarity-programmable. The BSP is fully static and operates at arbitrarily low clock frequencies. The
maximum operating frequency for ’54x devices up to 50 MIPs is CLKOUT. For higher-speed ’54x devices, the
maximum operating frequency is 50 MBps at 20 ns.
buffer misalignment (BMINT) interrupt (’549 only)
The BMINT interrupt is generated when a frame sync occurs and the ABU transmit or receive buffer pointer is
not at the top of the buffer address. This is useful for detecting several potential error conditions on the serial
interface, including extraneous and missed clocks and frame sync pulses. A BMINT interrupt, therefore,
indicates that one or more words may have been lost on the serial interface.
BMINT is useful for detecting buffer misalignment only when the buffer pointer(s) are initially loaded with the
top of buffer address, and a frame of data contains the same number of words as the buffer length. These are
the only conditions under which a frame sync occurring at a buffer address, other than the top of buffer, constitute
an error condition. In cases where these conditions are met, a frame sync always occurs when the buffer pointer
is at the top of buffer address, if the interface is functioning properly.
If BMINT is enabled under conditions other than those stated above, interrupts may be generated under
circumstances other than actual buffer misalignment. In these cases, BMINT should generally be masked in
the IMR register so that the processor will ignore this interrupt.
BMINT is available when operating auto-buffering mode with continuous transfers, the FIG bit cleared to 0, and
external serial clocks or frames.
The BSP0 and BSP1 BMINT bits in the IMR and IFR registers are bits 12 and 13, respectively, (bit 15 is the MSB),
and their interrupt vector locations are 070h and 074h, respectively.
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