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參數(shù)資料
| 型號： | TMS320M642AGDK7 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Video/Imaging Fixed-Point Digital Signal Processor |
| 中文描述： | 視頻/影像定點數(shù)字信號處理器 |
| 文件頁數(shù)： | 28/123頁 |
| 文件大小： | 1205K |
| 代理商： | TMS320M642AGDK7 |
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3.2.2
Memory Bus (Harvard Bus Architecture)
3.2.3
Peripheral Bus
3.2.4
Real-Time JTAG and Analysis
3.2.5
Flash
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
As with many DSP type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed "Harvard Bus", enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
Highest:
Data Writes
Program Writes
Data Reads
Program Reads
Fetches
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
Lowest:
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the
280x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16
address lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus
are supported on the 280x. One version only supports 16-bit accesses (called peripheral frame 2). The
other version supports both 16- and 32-bit accesses (called peripheral frame 1).
The 280x implements the standard IEEE 1149.1 JTAG interface. Additionally, the 280x supports real-time
mode of operation whereby the contents of memory, peripheral and register locations can be modified
while the processor is running and executing code and servicing interrupts. The user can also single step
through non-time critical code while enabling time-critical interrupts to be serviced without interference.
The 280x implements the real-time mode in hardware within the CPU. This is a unique feature to the
280x, no software monitor is required. Additionally, special analysis hardware is provided which allows the
user to set hardware breakpoint or data/address watch-points and generate various user-selectable break
events when a match occurs.
The F2808 contains 64K x 16 of embedded flash memory, segregated into four 16K X 16 sectors. The
F2806 has 32K X 16 of embedded flash, segregated into four 8K X 16 sectors. The F2801/UCD9501
devices contain 16K X 16 of embedded Flash (four 4K X 16 sectors). All three devices also contain a
single 1K x 16 of OTP memory at address range 0x3D 7800 - 0x3D 7BFF. The user can individually
erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not
possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other
sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance.
The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or
store data information. Note that addresses 0x3F7FF0 - 0x3F7FF5 are reserved for data variables and
should not contain program code.
28
Functional Overview
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