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參數資料
| 型號： | TMS320M642AZDK6 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1A, 52kHz (250kHz Max) Current Mode PWM Control Circuit with 16V UVLO Threshold and 48% Max Duty Cycle; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | 視頻/影像定點數字信號處理器 |
| 文件頁數： | 107/123頁 |
| 文件大?。?/td> | 1205K |
| 代理商： | TMS320M642AZDK6 |
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20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19
16
14
13
12
SPISTE
(A)
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5t
c(SPC)
(minimum) before the valid SPI clock
edge and remain low for at least 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 6-19. SPI Slave Mode External Timing (Clock Phase = 0)
Table 6-35. SPI Slave Mode External Timing (Clock Phase = 1)
(1)(2)(3)(4)
NO.
12
13
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
c(SPC)S
t
w(SPCH)S
t
w(SPCL)S
t
w(SPCL)S
t
w(SPCH)S
t
su(SOMI-SPCH)S
t
su(SOMI-SPCL)S
t
v(SPCH-SOMI)S
t
v(SPCL-SOMI)S
Cycle time, SPICLK
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
Setup time, SPISOMI before SPICLK low (clock polarity = 1
Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)
Valid time, SPISOMI data valid after SPICLK high (clock polarity =
1)
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK high (clock polarity =
0)
Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1)
8t
c(LCO)
0.5t
c(SPC)S
- 10
0.5t
c(SPC)S
- 10
0.5t
c(SPC)S
- 10
0.5t
c(SPC)S
- 10
0.125t
c(SPC)S
0.125t
c(SPC)S
0.75t
c(SPC)S
0.75t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
14
17
18
21
t
su(SIMO-SPCH)S
t
su(SIMO-SPCL)S
t
v(SPCH-SIMO)S
35
35
ns
ns
ns
22
0.5t
c(SPC)S
t
v(SPCL-SIMO)S
0.5t
c(SPC)S
ns
(1)
(2)
(3)
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
t
= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
(4)
Electrical Specifications
107
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