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TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
6-5
Power-on Reset
...................................................................................................................
91
Warm Reset
........................................................................................................................
92
Example of Effect of Writing Into PLLCR Register
...........................................................................
93
General-Purpose Output Timing
................................................................................................
93
Sampling Mode
....................................................................................................................
94
General-Purpose Input Timing
..................................................................................................
95
IDLE Entry and Exit Timing
......................................................................................................
96
STANDBY Entry and Exit Timing Diagram
....................................................................................
97
HALT Wake Up Using GPIOn
...................................................................................................
98
PWM Hi-Z Characteristics
.......................................................................................................
99
ADCSOCAO or ADCSOCBO Timing
.........................................................................................
101
External Interrupt Timing
.......................................................................................................
101
SPI Master Mode External Timing (Clock Phase = 0)
......................................................................
104
SPI Master External Timing (Clock Phase = 1)
..............................................................................
106
SPI Slave Mode External Timing (Clock Phase = 0)
........................................................................
107
SPI Slave Mode External Timing (Clock Phase = 1)
........................................................................
108
ADC Power-Up Control Bit Timing
............................................................................................
110
ADC Analog Input Impedance Model
.........................................................................................
111
Sequential Sampling Mode (Single-Channel) Timing
.......................................................................
112
Simultaneous Sampling Mode Timing
........................................................................................
113
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
List of Figures
5