參數(shù)資料
型號： TMS370C256FNA
元件分類： 8位微控制器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8位微控制器
文件頁數(shù)： 9/48頁
文件大?。?/td> 711K
代理商： TMS370C256FNA
TMS370Cx36
8-BIT MICROCONTROLLER
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
standby RAM module
The 256 byte standby RAM is general-purpose and powered through a separate V
CCSTBY
pin. The data stored
in this memory is protected against power failures on the main V
CC1
pins.
The standby RAM data is saved if the power failure on the main V
CC1
pins is detected externally and an external
reset is generated when V
CC1
falls below 4.3 V (see Figure 4). The external reset must remain low during the
entire power failures. The falling edge of the reset signal is internally detected to set the standby RAM in
low-power HALT mode. After the next power up, the RESET pin must be pulled high to get out of the HALT mode
of the standby RAM. In halt mode, the standby RAM consumes only leakage current.
4.3 Volt
VCC1
RESET
Standby RAM Locked in Halt Mode
Figure 4. Standby RAM Locked in Halt Mode
peripheral file (PF)
The TMS370Cx36 control registers contain all the registers necessary to operate the system and peripheral
modules on the device. The instruction set includes some instructions that access the PF directly. These
instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal
designator or P for a decimal designator. For example, the system-control register 0 (SCCR0) is located at
address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4
lists the TMS370Cx36 PF address map.
Table 4. TMS370Cx36 Peripheral File Address Map
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ADDRESS RANGE
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1000h–100Fh
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DESIGNATOR
P000–P00F
Reserved
PERIPHERAL FILE
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DESCRIPTION
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1020h–102Fh
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1040h–104Fh
P020–P02F
P040–P04F
Digital I/O port control registers
PACT registers
1030h–103Fh
P030–P03F
SPI registers
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