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參數(shù)資料
| 型號： | TMS370C777AYYZ |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 7/48頁 |
| 文件大?。?/td> | 711K |
| 代理商： | TMS370C777AYYZ |
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TMS370Cx36
8-BIT MICROCONTROLLER
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
central processing unit (CPU) (continued)
The ST, status-bit notation, and status-bit definitions are shown in Table 3.
Table 3. Status Registers
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ááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááá
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
program counter (PC)
The contents of the PC point to the memory location of the next instruction to be executed. The PC consists
of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These
registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address.
During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the PC. The PCH (MSbyte of the
PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is loaded with the
contents of memory location 7FFFh. Figure 2 shows this operation using an example value of 4000h as the
contents of the reset vector.
Memory
Program Counter (PC)
40
00
PCH
PCL
40
00
0000h
7FFEh
7FFFh
Figure 2. Program Counter After Reset
memory map
The TMS370Cx36 architecture is based on the Von Neuman architecture, where the program memory and data
memory share a common address space. All peripheral input/output is memory mapped in this same common
address space. As shown in Figure 3, the TMS370Cx36 provides memory-mapped RAM, ROM, EPROM, data
EEPROM, I/O pins, peripheral functions, and system-interrupt vectors.
The peripheral file contains all I/O port control, peripheral status and control, EEPROM, EPROM, and
system-wide control functions. The peripheral file is located between 1000h to 107Fh and is divided logically
into eight peripheral file frames of 16 bytes each. The eight PF frames consist of five control frames and three
reserved frames.Each on-chip peripheral is assigned to a separate frame through which peripheral control and
data information are passed.
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