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參數(shù)資料
| 型號： | TMS370C792NJT |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 15/48頁 |
| 文件大?。?/td> | 711K |
| 代理商： | TMS370C792NJT |
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TMS370Cx36
8-BIT MICROCONTROLLER
SPNS039B – JANUARY 1996 – REVISED FEBRUARY 1997
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
privileged operation and EEPROM write protection override (continued)
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system configuration registers section of Table 10.
P010.6
OSC POWER
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P011.2
SCCRO
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MEMORY DISABLE
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PF AUTO WAIT
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P03F.7
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P012.6
P012.7
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SPI STEST
P012.0
P012.1
P012.3
P012.4
PWRDWN/IDLE
HALT/STANDBY
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PRIVILEGE DISABLE
INT1 NMI
CPU STEST
BUS STEST
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P03F.5
P03F.6
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SPI ESPEN
SPI PRIORITY
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P040.0
P040.1
P040.2
P040.3
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PACT PRESCALE SELECT 0
PACT PRESCALE SELECT 1
PACT PRESCALE SELECT 2
PACT PRESCALE SELECT 3
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P04F.1
P04F.2
P04F.3
P04F.4
P04F.5
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PACT WD PRESCALE SELECT 1
PACT MODE SELECT
PACT GROUP 3 PRIORITY
PACT GROUP 2 PRIORITY
PACT GROUP 1 PRIORITY
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ADPRI
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P07F.6
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AD PRIORITY
low-power and IDLE modes
The TMS370Cx36 devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For
mask-ROM devices, low-power modes can be disabled permanently through a programmable contact when
the mask is manufactured.
The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping
the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes
is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The
HALT/STANDBY bit in SCCR2 controls the low-power mode selection.
In the STANDBY mode (HALT/STANDBY = 0), all CPU activity and most peripheral module activity is stopped;
however, the oscillator, internal clocks, the PACT counter, and the first PACT command entry remain active in
all modules. System processing is suspended until a qualified interrupt (hardware RESET or external interrupt
on INT1) is detected.
In the HALT mode (HALT/STANDBY = 1), the TMS370Cx36 is placed in its lowest power consumption mode.
The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is
suspended until a qualified interrupt (hardware RESET or external interrupt on the INT1) is detected. The
power-down mode-selection bits are summarized in Table 9.
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