- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368682 > TMS416100-70DGA x1 Fast Page Mode DRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | TMS416100-70DGA |
| 英文描述： | x1 Fast Page Mode DRAM |
| 中文描述： | x1快速頁(yè)面模式的DRAM |
| 文件頁(yè)數(shù)： | 10/25頁(yè) |
| 文件大?。?/td> | 437K |
| 代理商： | TMS416100-70DGA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)
TMS416100, TMS416100P
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS611 – FEBRUARY 1994
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’416100-60
’416100P-60
’416100-70
’416100P-70
’416100-80
’416100P-80
UNIT
MIN
30
MAX
MIN
35
MAX
MIN
40
MAX
tAWD
tCHR
tCRP
tCSH
tCSR
tCWD
tRAD
tRAL
tCAL
tRCD
tRPC
tRSH
tRWD
tCPW
tRASS
tRPS
tTAA
tTCPA
tTRAC
Delay time, column address to W low (read-write operation only)
ns
Delay time, RAS low to CAS high (CAS-before-RAS refresh only)
10
10
10
ns
Delay time, CAS high to RAS low
5
5
5
ns
Delay time, RAS low to CAS high
60
70
80
ns
Delay time, CAS low to RAS low (CAS-before-RAS refresh only)
5
5
5
ns
Delay time, CAS low to W low (read-write operation only)
15
18
20
ns
Delay time, RAS low to column address (see Note 14)
15
30
15
35
15
40
ns
Delay time, column address to RAS high
30
35
40
ns
Delay time, column address to CAS high
30
35
40
ns
Delay time, RAS low to CAS low (see Note 14)
20
45
20
52
20
60
ns
Delay time, RAS high to CAS low
0
0
0
ns
Delay time, CAS low to RAS high
15
18
20
ns
Delay time, RAS low to W low (read-write operation only)
60
70
80
ns
Delay time, W low after CAS precharge (read-write operation only)
35
40
45
ns
μ
s
ns
Pulse duration, self-refresh entry from RAS low
100
100
100
Pulse duration, RAS precharge after self refresh
110
130
150
Access time from address (test mode)
35
40
45
ns
Access time from column precharge (test mode)
40
45
50
ns
Access time from RAS (test mode)
65
75
85
ns
tREF
Refresh time interval
’416100
64
64
64
ms
’416100P
256
256
256
ms
tT
Transition time
3
30
3
30
3
30
ns
NOTE 14: The maximum value is specified only to assure access time.
PARAMETER MEASUREMENT INFORMATION
1.31 V
VCC = 5 V
CL = 100 pF
Output Under Test
Output Under Test
CL = 100 pF
(b) ALTERNATE LOAD CIRCUIT
(a) LOAD CIRCUIT
RL = 218
R1 = 828
R2 = 295
Figure 2. Load Circuits
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMS416100-70DJ | x1 Fast Page Mode DRAM |
| TMS416100-70DZ | x1 Fast Page Mode DRAM |
| TMS416100-80DGA | x1 Fast Page Mode DRAM |
| TMS416100-80DJ | x1 Fast Page Mode DRAM |
| TMS416100-80DZ | x1 Fast Page Mode DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS416100-70DJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| TMS416100-70DZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| TMS416100-80DGA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| TMS416100-80DJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
| TMS416100-80DZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 Fast Page Mode DRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。