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參數(shù)資料
| 型號： | TMS57014ADWBLE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | DUAL, SERIAL INPUT LOADING, 18-BIT DAC, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 11/17頁 |
| 文件大小： | 250K |
| 代理商： | TMS57014ADWBLE |
TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
ATT
3
I
Serial control data. ATT is a 16-bit word configured as LSB first (see Tables 2, 3, and 4).
AVDDL
26
I
Analog power supply (left channel)
AVDDR
17
I
Analog power supply (right channel)
AGNDL
24
I
Analog ground (left channel)
AGNDR
19
I
Analog ground (right channel)
BCK
10
I
Bit clock input. BCK clocks serial audio data into the device.
DATA
11
I
Audio data input. DATA can be configured as 16 or 18 bits with MSB or LSB first. DATA is 2s complement.
DVDD
15, 28
I
Digital supply
DGND
8
I
Digital ground
INIT
1
I
Reset. When INIT is brought low, the device is reset. The device is activated on the rising edge of INIT. The LRCK
signal must be applied to the device for a reset to occur.
LATCH
5
I
Serial-control data latch. Control data loads into the internal registers when LATCH is brought low.
LRCK
12
I
Left /right clock. LRCK signifies whether the serial data is associated with the left-channel DAC (when high) or the
right-channel DAC (when low).
MUTEL
13
O
Left-channel mute flag active. When the left channel is mute or the data through the channel remains at zero for the
system-register selected time, MUTEL is brought low.
MUTER
14
O
Right-channel mute flag active. When the right channel is mute or the data through the channel remains at zero for
the system-register selected time, MUTER is brought low.
L1
27
O
Left PWM output 1
L2
25
O
Left PWM output 2
R1
16
O
Right PWM output 1
R2
18
O
Right PWM output 2
SHIFT
4
I
Shift clock. SHIFT clocks the control data into the internal registers.
TEST
2, 7, 9
I
All TEST inputs should be tied low.
XIN
22
I
Master clock in. XIN derives all the key logic signals of the device. XIN runs at 512 Fs, where Fs is the sample rate.
XOUT
21
O
Master clock out
XVDD
20
I
Power supply for clock section
XGND
23
I
Ground for clock section
256FSO
6
O
System clock out. 256FSO reflects the master clock input divided by 2. The rate is 256Fs, where Fs is the sample
rate.
detailed description
The TMS57014A incorporates an interpolation impulse-response filter (FIR) and oversampled modulator.
The pulse-width modulation (PWM) digital output feeds into an external low-pass filter to recover the analog
audio signal.
Two control registers configure the device, the attenuation register controls the attenuation range and the
system register controls additional functions (see register set section).
reset / initialization
When INIT is brought low, an internal reset signal becomes active approximately 120 cycles of the sampling
frequency (Fs) after the falling edge of INIT. Under this condition, all internal circuits are initialized and the PWM
output is held at zero data (50% duty cycle). When INIT is brought high, the internal reset signal goes inactive
for a maximum of five LRCK periods after the rising edge of INIT. At this point, internal clocks are synchronous
with LRCK and the PWM output is valid (see Figure 1). The LRCK signal must be applied for proper initialization.
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