參數(shù)資料
型號： TMX320F2810PGFAEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 89/103頁
文件大?。?/td> 1341K
代理商： TMX320F2810PGFAEP
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
89
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
GPIO mux (continued)
Table 63. GPAQUAL Register Bit Definitions
BIT
NAME
TYPE
RESET
DESCRIPTION
7:0
QUALPRD
R/W
0:0
Specifies the qualification sampling period:
0x00
no qualification (just SYNC to SYSCLKOUT)
0x01
QUALPRD = SYSCLKOUT/2
0x02
QUALPRD = SYSCLKOUT/4
.
0xFF
QUALPRD = SYSCLKOUT/510
15:8
reserved
R=0
0:0
Notes:
1.
GPADIR bit = 0, configures corresponding GPIO pin as an input. GPADIR bit = 1, configures corresponding
GPIO pin as an output.
2.
The GPADAT, GPASET, GPACLEAR, GPATOGGLE registers have the same bit to I/O signal mapping as
the GPAMUX and GPADIR registers.
3.
The GPADAT register is a R/W register. Reading the register will reflect the current state of the input I/O
signal (after qualification). Writing to the register will set the corresponding state of any I/O signal configured
as an output.
4.
The GPASET register is a write only register (reads back 0). Writing a 1 to the corresponding bit of an I/O
signal will cause the I/O signal to go high. Writing a 0 will have no effect.
5.
The GPACLEAR register is a write only register (reads back 0). Writing a 1 to the corresponding bit of an
I/O signal will cause the I/O signal to go low. Writing a 0 will have no effect.
6.
The GPATOGGLE register is a write only register (reads back 0). Writing a 1 to the corresponding bit of an
I/O signal will cause the I/O signal to toggle. Writing a 0 will have no effect.
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