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參數(shù)資料
| 型號(hào)： | TOSCA |
| 英文描述： | TOSCA (STLC60134 STLC60135) ADSL MODEM CHIP SET |
| 中文描述： | 托斯卡（STLC60134 STLC60135）ADSL調(diào)制解調(diào)器芯片組 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 62K |
| 代理商： | TOSCA |
block drives, through the STLC60134’sintegrated
VCXO controller, the NT crystal oscillator which
comes up in an excellent synchronisation (less
than2ppm)between ATU-C and ATU-R.
FRAMING Functions
STLC60135 performs framing functions for ge-
neric and ATM TC sub layers.
ATMTC sub layerperformscell level functions:de-
lineation,idle cells or unassignedcells insertion/ex-
traction, payload scrambling, Header Error Correc-
tion(HEC)checkanddataframegeneration.
In order to comply with T1.413 Issue 2 rules and
full interoperability with other manufacturers’ mo-
dems (providing they guarantee compliance with
either Issue 1 or Issue 2) framing features (such
as interleaving and fast mode) are implemented
with programmableparameters.
ATM frames can be bypassed in order to carry
non-ATM bit streams, which makes the chip set
very fit for applications using dedicated framing
such as Frame-relay,etc.
STLC60135DTM modem main features:
Time-domain equalisation
Decimation, interpolation,
FFT and IFFT, with different length and sam-
pling rate at ATU-C and ATU-R side
Rotorand frequency-domainequalisation
Mapping/demapping
Trellis coding and decoding using Viterbi algo-
rithm
Error and noise monitoring on individualtones
Reed-Solomonencodingand decoding
(De)framing and (de) interleaving
Cell HEC generation/verification
Payload (de) scrambling
ATM cell insertion/extraction
Idle &/or Unassigned cell insertion/filtering
VPI/VCIfiltering
UTOPIA interface(Level 1 or 2)
Microcontroller interface with 16-bit multi-
plexed address/data bus and big/little endian
formatsupported
JTAGtest port
Single 3.3V supply,1.0W
PQFP144(28 x 28mmbody, 0.65mm pitch)
ADSL Modem control software
The ADSL transceiver is based on a programma-
ble DMT modem (STLC60135) whose configura-
tionis loaded by an externalcontroller.
Additionally the control functions, STMicroelec-
tronics provides the DTM modem software. The
software is written in C++ language, and is de-
signed to be portableto anyprocessor.
The driver has to be interfaced with a real time
OS kermel, it is compatible with any standard
product available on the market. The kernel man-
ages the tasksdedicated to modemsoftware.
The modem 5W core comes with three additional
two software modules: a Board Support Package
(BSP) and two Application Program Interfaces
(API). BSP manages the hardware dependent
features(i.e. interrupts,peripheral mapping).
APIs interface to the higher level application soft-
ware and to the OS.
ADSL Loop performances
The hereafter tables show the performances that
a system, which houses TOSCA, can achieve for
ANSI and ETSI loops. The following results refer
to an end-to end ADSLequipment with no exter-
nal disturbance.
ANSI Loop
(26awg)
Length
9Kft
12Kft
15Kft
Downstream
7.47 E +0.6
3.69 E +0.6
1.56 E +0.6
Upstream
1.05 E +06
9.37 E +05
7.25 E +05
ETSI Loop
(Loop 2, noise model A)
Length
2Km
4Km
5Km
Downstream
8.00 E +0.6
4.07 E +0.6
1.70 E +0.6
Upstream
8.32 E +05
6.72 E +05
4.72 E +05
USER HIGH LEVEL SOFTWARE
ADSL MANAGEMENT APPLICATION SW
OS INTERFACE
MODEM SW
BOARD SUPPORT PACKAGE
ADSL HARDWARE
D98TL392
Figure 4. Software Architecture.
TOSCA STLC60134/STLC60135
4/7
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