- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383962 > TP13054B (Texas Instruments, Inc.) Combination Codec/Filter(單片，串行接口，組合脈沖編碼譯碼器和濾波器) PDF資料下載
參數(shù)資料
| 型號(hào)： | TP13054B |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | Codec |
| 英文描述： | Combination Codec/Filter(單片，串行接口，組合脈沖編碼譯碼器和濾波器) |
| 中文描述： | 組合編解碼器/濾波器（單片，串行接口，組合脈沖編碼譯碼器和濾波器） |
| 文件頁(yè)數(shù)： | 3/15頁(yè) |
| 文件大?。?/td> | 338K |
| 代理商： | TP13054B |
第1頁(yè)第2頁(yè)當(dāng)前第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)
TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCMCODEC AND FILTER
SCTS042A – MAY 1990 – REVISED JULY 1994
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions
TERMINAL
NAME
ANLG GND
BCLKR/CLKSEL
DESCRIPTION
NO.
2
7
Analog ground. All signals are referenced to ANLG GND.
The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately,
BCLKR/CLKSEL can be a logic input that selects either 1.536 MHz/1.544 MHz or 2.048 MHz for the master clock in
the synchronous mode. BCLKX is used for both transmit and receive directions (see Table 1).
BCLKX
10
The bit clock that shifts out the PCM data on DX. BCLKX can vary from 64 kHz to 2.048 MHz, but must be synchronous
with MCLKX.
Receive data input. PCM data is shifted into DR following the FSR leading edge.
The 3-state PCM data output that in enabled by FSX
Receive frame-sync pulse input that enables BCLKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).
Transmit frame-sync pulse that enables BCLKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).
Analog output of the transmit input amplifier. GSX is used to externally set gain.
Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but should
be synchronous with MCLKX for best performance. When MCLKR is connected continuously low, MCLKX is selected
for all internal timing. When MCLKR is connected continuously high, the device is powered down.
DR
DX
FSR
6
11
5
FSX
12
GSX
MCLKR/PDN
14
8
MCLKX
TSX
VBB
VCC
VFRO
VFXI+
VFXI–
9
Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR.
Open-drain output that pulses low during the encoder time slot
Negative power supply pin. VBB = –5 V
±
5%
Positive power supply pin. VCC = 5 V
±
5%
Analog output of the receive filter
Noninverting input of the transmit input amplifier
Inverting input of the transmit input amplifier
13
1
4
3
16
15
Table 1. Selection of Master-Clock Frequencies
BCLKR/CLKSEL
MASTER-CLOCK FREQUENCY SELECTED
TP13054B, TP3054B
TP13057B, TP3057B
Clock Input
1.536 MHz or 1.544 MHz
2.048 MHz
Logic Input L
(sync mode only)
2.048 MHz
1.536 MHz or 1.544 MHz
Logic Input H (open)
(sync mode only)
1.536 MHz or 1.544 MHz
2.048 MHz
power up
Power-on reset circuitry initializes the TP3054B, TP3057B, TP13054B, and TP13057B when power is first
applied and places it into the power-down mode. DX and VFRO outputs go into high-impedance states and all
nonessential circuitry is disabled. A low level or clock applied to MCLKR/PDN powers up the device and
activates all circuits. DX, a 3-state PCM data output, will remain in the high-impedance state until the arrival of
the second FSX pulse.
To avoid any possible damage and reliability problems to these devices when applying power, the following
sequence should be followed:
1.
2.
3.
4.
Connect GND.
Connect the most negative voltage.
Connect the most positive voltage.
Connect the input signals.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TPA032D01DCAR | 10-W MONO CLASS-D AUDIO POWER AMPLIFIER |
| TPA032D01DCARG4 | 10-W MONO CLASS-D AUDIO POWER AMPLIFIER |
| TPA2013D1_1 | 2.7-W CONSTANT OUTPUT POWER CLASS-D AUDIO AMPLIFIER WITH INTEGRATED BOOST CONVERTER |
| TPA2013D1RGP | 2.7-W CONSTANT OUTPUT POWER CLASS-D AUDIO AMPLIFIER WITH INTEGRATED BOOST CONVERTER |
| TPA2013D1RGPT | 2.7-W CONSTANT OUTPUT POWER CLASS-D AUDIO AMPLIFIER WITH INTEGRATED BOOST CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP13054BDW | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13054BDWR | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13054BN | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP13057A | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP13057ADW | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。