Physical Dimensions inches (millimeters) Cavity Dual-In-Line Package (J) Order Number TP3054J or TP3057J" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� TP3054N-X/NOPB
寤犲晢锛� National Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 8/18闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC ENHANCED INTERFACE SER 16-DIP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 25
绯诲垪锛� COMBO®
椤炲瀷锛� PCM 绶ㄨВ纰煎櫒/婵炬尝鍣�
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶
ADC / DAC 鏁�(sh霉)閲忥細 1 / 1
涓夎绌嶅垎瑾�(di脿o)璁婏細 鐒�
闆诲 - 闆绘簮锛屾ā鎿細 ±5V
闆诲 - 闆绘簮锛屾暩(sh霉)瀛楋細 ±5V
宸ヤ綔婧害锛� -25°C ~ 125°C
瀹夎椤炲瀷锛� 閫氬瓟
灏佽/澶栨锛� 16-DIP锛�0.300"锛�7.62mm锛�
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 16-DIP
鍖呰锛� 绠′欢
鍏跺畠鍚嶇ū锛� *TP3054N-X
*TP3054N-X/NOPB
TP3054N-X
Physical Dimensions inches (millimeters)
Cavity Dual-In-Line Package (J)
Order Number TP3054J or TP3057J
NS Package Number J16A
Molded Small Outline Package (WM)
Order Number TP3054WM or TP3057WM
NS Package Number M16B
15
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
B37987M1683K000 CAP CER 0.068UF 100V 10% RADIAL
B37987M1473K000 CAP CER 0.047UF 100V 10% RADIAL
B37987M1333K000 CAP CER 0.033UF 100V 10% RADIAL
B37987M1223K000 CAP CER 0.022UF 100V 10% RADIAL
B37981M1153K000 CAP CER 0.015UF 100V 10% RADIAL
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
TP3054WM 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
TP3054WM/63SN 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
TP3054WM/NOPB 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
TP3054WMX 鍒堕€犲晢:NSC 鍒堕€犲晢鍏ㄧū:National Semiconductor 鍔熻兘鎻忚堪:Engineering Project Manager
TP3054WM-X 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

閲囪臣闇€姹�

(鑻ュ彧閲囪臣涓€姊濆瀷铏�(h脿o)锛屽～瀵竴琛屽嵆鍙�)

鐧�(f膩)甯冩垚鍔�锛佹偍鍙互绻肩簩(x霉)鐧�(f膩)甯冮噰璩笺€備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�(t谩i)锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

鐧�(f膩)甯冩垚鍔燂紒鎮ㄥ彲浠ョ辜绾�(x霉)鐧�(f膩)甯冮噰璩�銆備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�(t谩i)锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣

鎴戠殑鑱�(li谩n)绯绘柟寮�

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