Timing Specifications Unless otherwise noted limits printed in BOLD characters are guaranteed for V
參數(shù)資料
型號： TP3054WM-X/NOPB
廠商： National Semiconductor
文件頁數(shù)： 16/18頁
文件大小： 0K
描述： IC INTERFACE ENHANCED SER 16SOIC
標(biāo)準(zhǔn)包裝： 45
系列： COMBO®
類型： PCM 編解碼器/濾波器
數(shù)據(jù)接口： 串行
ADC / DAC 數(shù)量： 1 / 1
三角積分調(diào)變： 無
電壓 - 電源，模擬： ±5V
電壓 - 電源，數(shù)字： ±5V
工作溫度： -25°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC W
包裝： 管件
其它名稱： *TP3054WM-X
*TP3054WM-X/NOPB
TP3054WM-X
Timing Specifications Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC e
50V g5% VBB eb50V g5% TA e 0 Cto70 C by correlation with 100% electrical testing at TA e 25 C All other limits are
assured by correlation with other production tests andor product design and characterization All signals referenced to GNDA
Typicals specified at VCC e 50V VBB eb50V TA e 25 C All timing parameters are measured at VOH e 20V and VOL e
07V See Definitions and Timing Conventions section for test methods information
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1tPM
Frequency of Master Clocks
Depends on the Device Used and the
1536
MHz
BCLKR CLKSEL Pin
1544
MHz
MCLKX and MCLKR
2048
MHz
tRM
Rise Time of Master Clock
MCLKX and MCLKR
50
ns
tFM
Fall Time of Master Clock
MCLKX and MCLKR
50
ns
tPB
Period of Bit Clock
485
488
15725
ns
tRB
Rise Time of Bit Clock
BCLKX and BCLKR
50
ns
tFB
Fall Time of Bit Clock
BCLKX and BCLKR
50
ns
tWMH
Width of Master Clock High
MCLKX and MCLKR
160
ns
tWML
Width of Master Clock Low
MCLKX and MCLKR
160
ns
tSBFM
Set-Up Time from BCLKX High
First Bit Clock after the Leading
100
ns
to MCLKX Falling Edge
Edge of FSX
tSFFM
Set-Up Time from FSX High
Long Frame Only
100
ns
to MCLKX Falling Edge
tWBH
Width of Bit Clock High
VIHe22V
160
ns
tWBL
Width of Bit Clock Low
VILe06V
160
ns
tHBFL
Holding Time from Bit Clock
Long Frame Only
0
ns
Low to Frame Sync
tHBFS
Holding Time from Bit Clock
Short Frame Only
0
ns
High to Frame Sync
tSFB
Set-Up Time from Frame Sync
Long Frame Only
80
ns
to Bit Clock Low
tDBD
Delay Time from BCLKX High
Loade150 pF plus 2 LSTTL Loads
0
140
ns
to Data Valid
tDBTS
Delay Time to TSX Low
Loade150 pF plus 2 LSTTL Loads
140
ns
tDZC
Delay Time from BCLKX Low to
CLe0 pF to 150 pF
50
165
ns
Data Output Disabled
tDZF
Delay Time to Valid Data from
CLe0 pF to 150 pF
20
165
ns
FSX or BCLKX Whichever
Comes Later
tSDB
Set-Up Time from DR Valid to
50
ns
BCLKRX Low
tHBD
Hold Time from BCLKRX Low to
50
ns
DR Invalid
tSF
Set-Up Time from FSXR to
Short Frame Sync Pulse (1 Bit Clock
50
ns
BCLKXRLow
Period Long)
tHF
Hold Time from BCLKXR Low
Short Frame Sync Pulse (1 Bit Clock
100
ns
to FSXR Low
Period Long)
tHBFl
Hold Time from 3rd Period of
Long Frame Sync Pulse (from 3 to 8 Bit
100
ns
Bit Clock Low to Frame Sync
Clock Periods Long)
(FSX or FSR)
tWFL
Minimum Width of the Frame
64k Bits Operating Mode
160
ns
Sync Pulse (Low Level)
6
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