參數(shù)資料
型號: TP3057J-1
英文描述: Rocker Switch; Circuitry:DPDT; Switch Operation:On-On; Contact Current Max:16A; Switch Terminals:Quick Connect; Actuator Color:White; Leaded Process Compatible:Yes; Mounting Type:Panel RoHS Compliant: Yes
中文描述: A律編解碼器
文件頁數(shù): 4/16頁
文件大小: 250K
代理商: TP3057J-1
Functional Description
(Continued)
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors,
seeFigure 4. The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real-
ized. The op amp drives a unity-gain filter consisting of RC
active pre-filter, followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz. The output of
this filter directly drives the encoder sample-and-hold circuit.
The A/D is of companding type according to
m
-law
(TP3054) or A-law (TP3057) coding conventions. A preci-
sion voltage reference is trimmed in manufacturing to pro-
vide an input overload (t
MAX
) of nominally 2.5V peak (see
table of Transmission Characteristics). The FS
X
frame sync
pulse controls the sampling of the filter output, and then the
successive-approximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out through D
X
at the next FS
X
pulse. The total encoding delay will be ap-
proximately 165
m
s (due to the transmit filter) plus 125
m
s
(due to encoding delay), which totals 290
m
s. Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration.
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz. The decoder is A-law (TP3057) or
m
-law (TP3054) and the 5th order low pass filter corrects for
the sin x/x attenuation due to the 8 kHz sample/hold. The
filter is then followed by a 2nd order RC active post-filter/
power amplifer capable of driving a 600
X
load to a level of
7.2 dBm. The receive section is unity-gain. Upon the occur-
rence of FS
R
, the data at the D
R
input is clocked in on the
falling edge of the next eight BCLK
R
(BCLK
X
) periods. At
the end of the decoder time slot, the decoding cycle begins,
and 10
m
s later the decoder DAC output is updated. The
total decoder delay is
E
10
m
s (decoder update) plus
110
m
s (filter delay) plus 62.5
m
s (
(/2
frame), which gives
approximately 180
m
s.
4
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相關(guān)代理商/技術(shù)參數(shù)
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