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參數(shù)資料
| 型號： | TP3057V-X |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE ENHANCED SER 20PLCC |
| 標準包裝： | 40 |
| 類型： | PCM 編解碼器/濾波器 |
| 數(shù)據(jù)接口： | 串行 |
| ADC / DAC 數(shù)量： | 1 / 2 |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，模擬： | ±5V |
| 電壓 - 電源，數(shù)字： | ±5V |
| 工作溫度： | -25°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應商設備封裝： | 20-PLCC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | *TP3057V-X |
Functional Description (Continued)
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors
see
Figure 4 The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real-
ized The op amp drives a unity-gain filter consisting of RC
active pre-filter followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz The output of
this filter directly drives the encoder sample-and-hold circuit
The AD is of companding type according to m-law
(TP3054) or A-law (TP3057) coding conventions A preci-
sion voltage reference is trimmed in manufacturing to pro-
vide an input overload (tMAX) of nominally 25V peak (see
table of Transmission Characteristics) The FSX frame sync
pulse controls the sampling of the filter output and then the
successive-approximation encoding cycle begins The 8-bit
code is then loaded into a buffer and shifted out through DX
at the next FSX pulse The total encoding delay will be ap-
proximately 165 ms (due to the transmit filter) plus 125 ms
(due to encoding delay) which totals 290 ms Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz The decoder is A-law (TP3057) or
m
-law (TP3054) and the 5th order low pass filter corrects for
the sin xx attenuation due to the 8 kHz samplehold The
filter is then followed by a 2nd order RC active post-filter
power amplifer capable of driving a 600X load to a level of
72 dBm The receive section is unity-gain Upon the occur-
rence of FSR the data at the DR input is clocked in on the
falling edge of the next eight BCLKR (BCLKX) periods At
the end of the decoder time slot the decoding cycle begins
and 10 ms later the decoder DAC output is updated The
total decoder delay is E 10 ms (decoder update) plus
110 ms (filter delay) plus 625 ms(
frame) which gives
approximately 180 ms
4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3057WM | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3057WM/63SN | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3057WM/NOPB | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3057WMNOPB | 制造商:National Semiconductor 功能描述:Audio Codec 1ADC / 2DAC 16-Pin SOIC W Tube 制造商:National Semiconductor 功能描述:Audio Codec 1ADC / 2DAC 16-Pin SOIC Tube |
| TP3057WMX | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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