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參數(shù)資料
| 型號： | TP3067WM/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE ENHANCED SER 20SOIC |
| 標準包裝： | 36 |
| 類型： | PCM 編解碼器/濾波器 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 8 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，模擬： | ±5V |
| 電壓 - 電源，數(shù)字： | ±5V |
| 工作溫度： | -25°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC |
| 包裝： | 管件 |
| 其它名稱： | *TP3067WM *TP3067WM/NOPB TP3067WM |
Functional Description (Continued)
table of Transmission Characteristics) The FSX frame sync
pulse controls the sampling of the filter output and then the
successive-approximation encoding cycle begins The 8-bit
code is then loaded into a buffer and shifted out through DX
at the next FSX pulse The total encoding delay will be ap-
proximately 165 ms (due to the transmit filter) plus 125 ms
(due to encoding delay) which totals 290 ms Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz The decoder is A-law (TP3067) or
m
-law (TP3064) and the 5th order low pass filter corrects for
the sin xx attenuation due to the 8 kHz samplehold The
filter is then followed by a 2nd order RC active post-filter
with its output at VFRO The receive section is unity-gain
but gain can be added by using the power amplifiers Upon
the occurrence of FSR the data at the DR input is clocked in
on the falling edge of the next eight BCLKR (BCLKX) peri-
ods At the end of the decoder time slot the decoding cycle
begins and 10 ms later the decoder DAC output is updated
The total decoder delay is E10 ms (decoder update) plus
110 ms (filter delay) plus 625 ms(
frame) which gives
approximately 180 ms
RECEIVE POWER AMPLIFIERS
Two inverting mode power amplifiers are provided for direct-
ly driving a matched line interface transformer The gain of
the first power amplifier can be adjusted to boost the g25V
peak output signal from the receive filter up to g33V peak
into an unbalanced 300X load or g40V into an unbal-
anced 15 kX load The second power amplifier is internally
connected in unity-gain inverting mode to give 6 dB of signal
gain for balanced loads
Maximum power transfer to a 600X subscriber line termina-
tion is obtained by differentially driving a balanced trans-
former with a S2 1 turns ratio as shown in
Figure 4 A total
peak power of 156 dBm can be delivered to the load plus
termination
ENCODING FORMAT AT DX OUTPUT
TP3064
TP3067
m-Law
A-Law
(Includes Even Bit Inversion)
VIN eaFull-Scale
1
000000010101010
VIN e 0V
1
111111111010101
0
111111101010101
VIN ebFull-Scale
0
000000000101010
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TP3054WM-X/NOPB | IC INTERFACE ENHANCED SER 16SOIC |
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| VI-263-CU | CONVERTER MOD DC/DC 24V 200W |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP30-68 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:TRISILTM |
| TP3068J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
| TP3068N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
| TP30-68RL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRISIL |
| TP3068V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
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