參數(shù)資料
型號: TPA0162PWPG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻控制
英文描述: 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PDSO24
封裝: GREEN, PLASTIC, HTSSOP-24
文件頁數(shù): 9/34頁
文件大?。?/td> 812K
代理商: TPA0162PWPG4
www.ti.com
Changing Volume When Using the Internal Clock
f
CLK +
4.7
10–6
C
CLK
(1)
CLK
VOLUME
40 cycles
20 cycles
12 cycles
4 cycles per step
4 cycles
UP
8 cycles
Changing Volume When Using the External Clock (Microprocessor Mode)
TPA0162
SLOS249E – JUNE 1999 – REVISED SEPTEMBER 2004
If using the internal clock, the maximum clock frequency is 500 Hz and the recommended frequency is 100 Hz
using a 47-nF capacitor. Use Equation 1 to calculate the clock frequency if using a capacitor to generate the
clock.
When the desired volume-control signal is pulled low for four clock cycles, the volume increments by one step,
followed by a short delay. This delay decreases the longer the line is held low, eventually reaching a delay of
zero. The delay allows the user to pull the UP or DOWN terminal low once for one volume change, or hold down
to ramp several volume changes. The delay is optimally configured for push button volume control.
Holding either UP or DOWN low continuously causes the volume to change at an exponentially increasing rate.
When fCLK = 100 Hz, the first change in the volume occurs approximately 40 ms after either pin is initially pulled
low. If the pin stays low for approximately 400 more ms, the volume changes again. The next change occurs 200
ms after this change. The fourth change occurs 120 ms after the third change. The fifth volume change occurs
80 ms after the fourth change. Thereafter, the volume changes at 1/4 the rate of the clock (every 40 ms).
Each cycle is registered on the rising clock edge and the volume is changed after the rising edge.
Figure 32 shows increasing volume using UP, however, the volume is decreased using DOWN with the same
timing.
Figure 32. Internal Clock Timing Diagram
The user may remove the capacitor and run the external clock directly into the clock pin to override the internal
clock generator. The maximum clock frequency is 10 kHz if using an external clock; however, a clock frequency
less than 200 Hz is recommended in normal operation so the gain does not change too quickly causing a pop at
the output. A 5-V, 50% duty-cycle clock must be used because the trip levels are 0.5 V and 4.5 V. The
recommended way to adjust the volume is to use a gated clock and hold UP or DOWN low and cycle the clock
pin four times to adjust the volume. The volume change is clocked in at the rising edge, so CLK should be held
low when not changing volume. No delay is added when using an external clock, so it is very important to input
only four clock cycles per volume change. Additional clock cycles per volume change are added to the next
volume change. For example, if five clock cycles are input while UP is held low the first volume change, the
volume change occurs after the third clock cycle the next time UP is held low. The figure below shows how
volume increases with UP when an external clock is used. The sample and hold times for UP and DOWN are
100 ns. The same timing applies if using an external clock and decreasing the volume with DOWN.
17
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