參數(shù)資料
型號: TPA0172PWP
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻控制
英文描述: 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PDSO24
封裝: GREEN, PLASTIC, HTSSOP-24
文件頁數(shù): 22/36頁
文件大?。?/td> 885K
代理商: TPA0172PWP
TPA0172
2W STEREO AUDIO POWER AMPLIFIER
WITH I2C BUS
SLOS327C AUGUST 2000 REVISED MAY 2001
29
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
mask register operation
The mask register allows the user to select whether SHUTDOWN, SE/BTL, and PC-BEEP are to be controlled
by the external pins or by the internal control register. Since PC-BEEP does not have an external control pin
available, writing a 1 to this bit will disable all internal register control and place the PC-BEEP input in auto-detect
mode. When a bit is set, the corresponding internal control register bit is masked or ignored and the external
pin controls the operating mode. Conversely, when a bit is set to 0, the corresponding external pin is disabled
and the internal control register bit determines the operating mode. For example, writing XXXXX010 to the
register allows the control register to control the operation of the PC-BEEP input and SHUTDOWN, while
allowing the external pin to control SE/BTL.
The MSB of the mask register is read-only. It is set when the TPA0172 is executing its power-up sequence and
is set to 0 upon completion of the sequence and during normal operation. To avoid any unwanted clicks or pops,
the gain registers should not be changed while this bit is set.
control register operation
Each bit of the control register allows the user to control the operating mode of the TPA0172, as shown in
Table 9.
Table 9. Control Register Bit Assignments
BIT
FUNCTION
VALUE
RESULT
0
SHUTDOWN
0
1
Normal operation
Shutdown mode
1
HP/LINE
0
1
Line inputs selected
Headphone inputs selected
2
Reserved
0
3
Mute
0
1
Normal operation
Mute mode
4
Reserved
1
5
SE/BTL
0
1
BTL mode
SE mode
6
Gain register select
0
1
Use BTL gain registers
Use SE gain registers
7
PC-BEEP enable
0
1
Auto-detect PC-BEEP
PC-BEEP always on
Bit 0 operates in the same manner as the external SHUTDOWN pin, but the logic is active high in the internal
register.
Bit 1 allows the user to select the input source. If bit 1 of the mask register is set, however, the HP/LINE function
is tied to the external SE/BTL pin.
Bit 2 should always be set to 0. Reserved for future functionality.
Bit 3 performs the same mute function as setting either bit 6 or 7 in the gain registers.
Bit 4 should always be set to 1. Reserved for future functionality.
Bit 5 operates in the same manner as the external SE/BTL pin.
Bit 6 allows the user to select which gain registers will determine the gain settings for each channel. For example,
the amplifier may be configured to operate in SE mode, but with the gain settings taken from the BTL registers.
This function is tied to the SE/BTL pin if bit 1 of the mask register is set, which results in the SE gain registers
controlling the gain in SE mode, and the BTL registers controlling the gain in BTL mode.
Bit 7 allows the user to either auto-detect a signal at the PC-BEEP input or manually override that input to always
be on.
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