參數(shù)資料
型號: TPA3002D2PHPRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻控制
英文描述: 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PQFP48
封裝: GREEN, PLASTIC, HTQFP-48
文件頁數(shù): 22/40頁
文件大?。?/td> 735K
代理商: TPA3002D2PHPRG4
TPA3002D2
SLOS402C DECEMBER 2002 REVISED JANUARY 2004
www.ti.com
29
PRINTED CIRCUIT BOARD (PCB) LAYOUT
Because the TPA3002D2 is a class-D amplifier that switches at a high frequency, the layout of the printed circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
D Decoupling capacitors — As described on page 28, the high-frequency 0.1-F decoupling capacitors
should be placed as close to the PVCC (pin 14, 15, 22, 23, 38, 39, 46, 47) and AVCC (pin 33) terminals
as possible. The V2P5 (pin 4) capacitor, AVDD (pin 29) capacitor, and VCLAMP (pins 25, 36) capacitor
should also be placed as close to the device as possible. Large (10
F or greater) bulk power supply
decoupling capacitors should be placed near the TPA3002D2 on the PVCCL, PVCCR, and AVCC
terminals.
D Grounding — The AVCC (pin 33) decoupling capacitor, AVDD (pin 29) capacitor, V2P5 (pin 4) capacitor,
COSC (pin 28) capacitor, and ROSC (pin 27) resistor should each be grounded to analog ground (AGND,
pin 26 and pin 30). The PVCC (pin 9 and pin 16) decoupling capacitors should each be grounded to power
ground (PGND, pins 18, 19, 42, 43). Analog ground and power ground may be connected at the
PowerPAD, which should be used as a central ground connection or star ground for the TPA3002D2.
Basically, an island should be created with a single connection to PGND at the PowerPAD.
D Output filter — The ferrite EMI filter (Figure 34) should be placed as close to the output terminals as
possible for the best EMI performance. The LC filter (Figure 33 should be placed close to the outputs. The
capacitors used in both the ferrite and LC filters should be grounded to power ground.
D PowerPAD — The PowerPAD must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the PowerPAD thermal land should be 5 mm by 5 mm (197 mils by 197 mils).
The PowerPAD size measures 4,55 x 4,55 mm. Four rows of solid vias (four vias per row, 0,3302 mm or
13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a
solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid
vias, not thermal relief or webbed vias. For additional information, please refer to the PowerPAD Thermally
Enhanced Package application note (SLMA002).
For an example layout, refer to the TPA3002D2 Evaluation Module (TPA3002D2EVM) User Manual
(SLOU151). Both the EVM user manual and the PowerPAD application note are available on the TI web site
at http://www.ti.com.
15
20
25
30
1
1.5
2
2.5
3
3.5
4
4.5
5
Copper Area sq. Inches
THERMAL RESISTANCE
vs
COPPER AREA 2-LAYER PCB
35
12
3
4
5
15
20
25
30
35
Copper Area sq. Inches
THERMAL RESISTANCE
vs
COPPER AREA 4-LAYER PCB
Thermal
Resistance
JAθ
C/W
°
Thermal
Resistance
JAθ
C/W
°
Figure 38. Thermal Resistance
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