參數(shù)資料
型號(hào)： TPA3005D2PHP
廠商： Texas Instruments
文件頁數(shù)： 28/31頁
文件大?。?/td> 0K
描述： IC AMP AUDIO PWR 6W STER 48TQFP
標(biāo)準(zhǔn)包裝： 250
類型： D 類
輸出類型： 2 通道（立體聲）
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： 6W x 2 @ 8 歐姆
電源電壓： 8.5 V ~ 18 V
特點(diǎn)： 差分輸入，短路保護(hù)和熱保護(hù)，關(guān)機(jī)
安裝類型： 表面貼裝
供應(yīng)商設(shè)備封裝： 48-HTQFP（7x7）
封裝/外殼： 48-TQFP 裸露焊盤
包裝： 托盤
配用： 296-18924-ND - EVAL MODULE FOR TPA3005D2
SLOS427A – MAY 2004 – REVISED AUGUST 2010
www.ti.com
TERMINAL FUNCTIONS
PIN NAME
PIN NUMBER
I/O
DESCRIPTION
AGND
26, 30
-
Analog ground for digital/analog cells in core
AVCC
33
-
High-voltage analog power supply, not connected internally to PVCCR or PVCCL
5-V Regulated output for use by internal cells and GAIN0, GAIN1 pins only. Not
AVDD
29
O
specified for driving other external circuitry.
AVDDREF
7
O
5-V Reference output—connect to gain setting resistor or directly to GAIN0, GAIN1.
BSLN
13
-
Bootstrap I/O for left channel, negative high-side FET
BSLP
24
-
Bootstrap I/O for left channel, positive high-side FET
BSRN
48
-
Bootstrap I/O for right channel, negative high-side FET
BSRP
37
-
Bootstrap I/O for right channel, positive high-side FET
COSC
28
I/O
I/O for charge/discharging currents onto capacitor for ramp generator.
GAIN0
9
I
Gain select least significant bit. TTL logic levels with compliance to AVDD.
GAIN1
10
I
Gain select most significant bit. TTL logic levels with compliance to AVDD.
LINN
6
I
Negative audio input for left channel
LINP
5
I
Positive audio input for left channel
LOUTN
16, 17
O
Class-D 1/2-H-bridge negative output for left channel
LOUTP
20, 21
O
Class-D 1/2-H-bridge positive output for left channel
8, 11, 12, 31,
NC
-
No internal connection
32, 34, 35
PGNDL
18, 19
-
Power ground for left channel H-bridge
PGNDR
42, 43
-
Power ground for right channel H-bridge
Power supply for left channel H-bridge (internally connected to pins 22 and 23), not
PVCCL
14, 15
-
connected to PVCCR or AVCC.
Power supply for left channel H-bridge (internally connected to pins 14 and 15), not
PVCCL
22, 23
-
connected to PVCCR or AVCC.
Power supply for right channel H-bridge (internally connected to pins 46 and 47),
PVCCR
38, 39
-
not connected to PVCCL or AVCC.
Power supply for right channel H-bridge (internally connected to pins 38 and 39),
PVCCR
46, 47
-
not connected to PVCCL or AVCC.
RINP
3
I
Positive audio input for right channel
RINN
2
I
Negative audio input for right channel
ROSC
27
I/O
I/O current setting resistor for ramp generator.
ROUTN
44, 45
O
Class-D 1/2-H-bridge negative output for right channel
ROUTP
40, 41
O
Class-D 1/2-H-bridge positive output for right channel
Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with
SHUTDOWN
1
I
compliance to VCC.
VCLAMPL
25
-
Internally generated voltage supply for left channel bootstrap capacitors.
VCLAMPR
36
-
Internally generated voltage supply for right channel bootstrap capacitors.
V2P5
4
O
2.5-V Reference for analog cells.
Connect to AGND and PGND—should be the center point for both grounds. Internal
Thermal Pad
-
resistive connection to AGND.
TYPICAL CHARACTERISTICS
Table 1. TABLE OF GRAPHS
FIGURE
THD+N
Total harmonic distortion + noise
vs Output power
1, 2
vs Frequency
3, 4, 5, 6
Closed loop response
7
ICC
Supply current
vs Output power
8
Efficiency
vs Output power
9
Output power
vs Supply voltage
10, 11
6
Copyright 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPA3005D2
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