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參數(shù)資料
| 型號： | TPA3200D1DCPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 12.8 W, 1 CHANNEL, AUDIO AMPLIFIER, PDSO44 |
| 封裝： | GREEN, PLASTIC, HTSSOP-44 |
| 文件頁數(shù)： | 5/29頁 |
| 文件大?。?/td> | 1083K |
| 代理商： | TPA3200D1DCPRG4 |
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SYSTEM CLOCK INPUT
t(SCKH)
t(SCY)
System Clock (SCK)
t(SCKL)
2.0 V
0.8 V
H
L
AUDIO SERIAL INTERFACE
TPA3200D1
SLOS442A – MAY 2005 – REVISED JULY 2005
APPLICATION INFORMATION (continued)
The TPA3200D1 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma
modulators. The system clock is applied at the SCLK input (pin 44). Table 1 shows examples of system clock
frequencies for common audio sampling rates.
Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase-jitter and noise. TI’s PLL170x family of multiclock generators is an excellent
choice for providing the TPA3200D1 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLE
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
FREQUENCY
128 fS
192 fS
256 fS
384 fS
512 fS
768 fS
1152fS
8 kHz
1.0240
1.5360
2.0480
3.0720
4.0960
6.1440
9.2160
16 kHz
2.0480
3.0720
4.0960
6.1440
8.1920
12.2880
18.4320
32 kHz
4.0960
6.1440
8.1920
12.2880
16.3840
24.5760
36.8640
44.1 kHz
5.6448
8.4672
11.2896
16.9344
22.5792
33.8688
(1)
48 kHz
6.1440
9.2160
12.2880
18.4320
24.5760
36.8640
(1)
88.2 kHz
11.2896
16.9344
22.5792
33.8688
45.1584
(1)
96 kHz
12.2880
18.4320
24.5760
36.8640
49.1520
(1)
192 kHz
24.5760
36.8640
49.1520
See (1)
(1)
This system clock rate is not supported for the given sampling frequency.
Figure 18. System Clock Input Timing
PARAMETERS
SYMBOL
MIN
TYP
MAX
UNITS
System clock pulse duration, high
t(SCKH)
7
System clock pulse duration, low
t(SCKL)
ns
System clock pulse cycle time
t(SCY)
7
See (1)
(1)
1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, 1/768 fS, or 1/1152 fS
The audio serial interface for the TPA3200D1 consists of a 3-wire synchronous serial port. It includes LRCK (pin
4), BCK (pin 1), and DATA (pin 3). BCK is the serial audio bit clock, and it is used to clock the serial data present
on DATA into the serial shift register of the audio interface. Serial data is clocked into the TPA3200D1 on the
rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latch serial data into the internal
registers of the serial audio interface.
Both LRCK and BCK should be synchronous to the system clock. Ideally, it is recommended that LRCK and BCK
be derived from the system clock input, SCK. LRCK is operated at the sampling frequency, fS. BCK can be
operated at 32, 48, or 64 times the sampling frequency for standard and left-justified formats. BCK can be
operated at 48 or 64 times the sampling frequency for the I2S format.
Internal operation of the TPA3200D1 is synchronized with LRCK. Accordingly, internal operation is held when the
sampling rate clock of LRCK is changed or when SCK and/or BCK is interrupted for a 3-bit clock cycle or longer.
If SCK, BCK, and LRCK are provided continuously after this held condition, the internal operation is
re-synchronized automatically in a period of less than 3/fS. External resetting is not required.
13
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