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    參數(shù)資料
    型號: TPA5051RSARG4
    廠商: TEXAS INSTRUMENTS INC
    元件分類: 消費(fèi)家電
    英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC16
    封裝: 4 X 4 MM, GREEN, PLASTIC, QFN-16
    文件頁數(shù): 23/23頁
    文件大小: 812K
    代理商: TPA5051RSARG4
    www.ti.com
    A6
    A5
    A0 R/W ACK A7
    A6
    A5
    A4
    A0 ACK
    A6
    A5
    A0
    ACK
    Start
    Condition
    Stop
    Condition
    Acknowledge
    I2CDeviceAddressand
    Read/WriteBit
    Register
    DataByte
    D7
    D6
    D1
    D0 ACK
    I2CDeviceAddressand
    Read/WriteBit
    Not
    Acknowledge
    R/W
    A1
    RepeatStart
    Condition
    MULTIPLE-BYTE READ
    A6
    A0
    ACK
    Acknowledge
    I2CDeviceAddressand
    Read/WriteBit
    R/W
    A6
    A0
    R/W ACK
    A0 ACK
    D7
    D0
    ACK
    Start
    Condition
    Stop
    Condition
    Acknowledge
    LastDataByte
    ACK
    FirstDataByte
    RepeatStart
    Condition
    Not
    Acknowledge
    I2CDeviceAddressand
    Read/WriteBit
    Register
    OtherDataBytes
    A7
    A6
    A5
    D7
    D0 ACK
    Acknowledge
    D7
    D0
    TPA5051 Operation
    VDD
    DATA1
    LRCLK1
    BCLK1
    GND
    DATA_OUT1
    SDA
    SCL
    ADD0
    ADD1
    ADD2
    GND
    3.3V
    0.1 F
    m
    Digital Audio1
    WordClock1
    BitClock1
    Delayed Audio1
    I CClock
    2
    I CData
    2
    I C Address
    Select
    2
    Digital Audio2
    WordClock2
    BitClock2
    DATA2
    LRCLK2
    BCLK2
    DATA_OUT2
    Delayed Audio2
    SLOS497A – JUNE 2006 – REVISED JULY 2006
    Figure 8. Single-Byte Read Transfer
    A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
    are transmitted by the TPA5051 to the master device as shown in Figure 9. With the exception of the last data
    byte, the master device responds with an acknowledge bit after receiving each data byte.
    Figure 9. Multiple-Byte Read Transfer
    The following sections describe the registers configurable via I2C commands for the TPA5051.
    Only a single decoupling capacitor (0.1
    F–1 F) is required across VDD and GND. The ADDx terminals can be
    directly connected to VDD or GND. Table 1 describes the I2C addresses selectable via the ADDx terminals. A
    schematic implementation of the TPA5051 is shown in Figure 10.
    Figure 10. TPA5051 Schematic
    9
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