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參數(shù)資料
| 型號： | TPA5051RSATG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC16 |
| 封裝： | 4 X 4 MM, GREEN, PLASTIC, QFN-16 |
| 文件頁數(shù)： | 2/23頁 |
| 文件大小： | 812K |
| 代理商： | TPA5051RSATG4 |
www.ti.com
SERIAL CONTROL INTERFACE REGISTER SUMMARY
CONTROL REGISTER (0x01, 0x09)
AUDIO DELAY REGISTERS (0x02–0x05, 0x0A–0x0D)
SLOS497A – JUNE 2006 – REVISED JULY 2006
Table 2. Serial Control Register Summary
REGISTER
REGISTER NAME
NO. OF
CONTENTS
INITIALIZATION
BYTES
VALUE
0x01(1)
Control Register
1
Description shown in subsequent section
00
0x02(1)
Right Delay Upper (5 bits)
1
Description shown in subsequent section
00
0x03(1)
Right Delay Lower (8 bits)
1
Description shown in subsequent section
00
0x04(1)
Left Delay Upper (5 bits)
1
Description shown in subsequent section
00
0x05(1)
Left Delay Lower (8 bits)
1
Description shown in subsequent section
00
0x06(1)
Frame Delay
1
Description shown in subsequent section
00
0x07(1)
RJ Packet Length
1
Description shown in subsequent section
00
0x08(1)
Complete Update
1
Description shown in subsequent section
00
0x09(2)
Control Register
1
Description shown in subsequent section
00
0x0A(2)
Right Delay Upper (5 bits)
1
Description shown in subsequent section
00
0x0B(2)
Right Delay Lower (8 bits)
1
Description shown in subsequent section
00
0x0C(2)
Left Delay Upper (5 bits)
1
Description shown in subsequent section
00
0x0D(2)
Left Delay Lower (8 bits)
1
Description shown in subsequent section
00
0x0E(2)
Frame Delay
1
Description shown in subsequent section
00
0x0F(2)
RJ Packet Length
1
Description shown in subsequent section
00
0x10(2)
Complete Update
1
Description shown in subsequent section
00
(1)
I2C registers for serial data channel 1
(2)
I2C registers for serial data channel 2
The control register allows the user to mute a specific audio channel. It is also used to specify the data type (I2S,
Right-Justified, or Left-Justified).
Table 3. Control Registers (0x01, 0x09)(1)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
X
–
Left and Right channel are active.
0
1
X
–
Left channel is MUTED.
1
0
X
–
Right channel is MUTED.
1
X
–
Left and Right channel are MUTED.
–
X
0
I2S data format
–
X
0
1
Right-justified data format (see PACKET LENGTH register 0x07)
–
X
1
0
Left-justified data format
–
X
1
Bypass mode – data is passed straight through without delay.
(1)
Default values are in bold.
The audio delay for the left and right channels is fixed by writing a total of 13 bits (2 byte transfer) to upper and
lower registers as specified in Table 1. A multiple byte transfer should be performed starting with the control
register and following with 4 bytes to fill the upper and lower registers associated with right/left channel delay.
The decimal value of D0–D13 equals the number of samples to delay. The maximum number of delayed
samples per channel is 4095 for the TPA5051. This equates to 85.3 ms ([4095
× (1/Fs)] at 48 kHz) of delay per
channel.
10
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| TPA5052 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:STEREO DIGITAL AUDIO LIP-SYNC DELAY |
| TPA5052EVM | 功能描述:音頻 IC 開發(fā)工具 AUD DELAY DEVICE RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| TPA5052RSAR | 功能描述:音頻 DSP St Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
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