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參數(shù)資料
型號(hào): TPA6140A2YFFEVM
廠商: Texas Instruments
文件頁(yè)數(shù): 14/30頁(yè)
文件大?。?/td> 0K
描述: EVALUATION MODULE FOR TPA6140A2
視頻文件: TPA6140A2 Demonstration
特色產(chǎn)品: TPA6140A2 Class G DirectPath? Stereo Headphone Amplifier
標(biāo)準(zhǔn)包裝: 1
系列: DirectPath™
放大器類型: G 類
輸出類型: 耳機(jī),2-通道(立體聲)
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量: 32mW x 2 @ 32 歐姆
電源電壓: 2.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
板類型: 完全填充
已用 IC / 零件: TPA6140A2
已供物品: 板,CD
產(chǎn)品目錄頁(yè)面: 878 (CN2011-ZH PDF)
配用: WM2582-ND - EVALDI EARBUDS TYPE Y
相關(guān)產(chǎn)品: 296-24303-6-ND - IC AMP AUDIO 25MW STER 16DSBGA
296-24303-1-ND - IC AMP AUDIO 25MW STER 16DSBGA
296-24303-2-ND - IC AMP AUDIO 25MW STER 16DSBGA
296-24237-6-ND - IC AMP AUDIO 25MW STER 16DSBGA
296-24237-1-ND - IC AMP AUDIO 25MW STER 16DSBGA
296-24237-2-ND - IC AMP AUDIO 25MW STER 16DSBGA
其它名稱: 296-24299
Register
A6
A5
A0 R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A0
ACK
Start
Condition
Stop
Condition
Acknowledge
I2CDeviceAddressand
Read/WriteBit
Register
DataByte
D7
D6
D1
D0 ACK
I2CDeviceAddressand
Read/WriteBit
Not
Acknowledge
R/W
A1
RepeatStart
Condition
A6
A0
ACK
Acknowledge
I2CDeviceAddressand
Read/WriteBit
R/W
A6
A0
R/W ACK
A0 ACK
D7
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
LastDataByte
ACK
FirstDataByte
RepeatStart
Condition
Not
Acknowledge
I2CDeviceAddressand
Read/WriteBit
Register
OtherDataBytes
A7
A6
A5
D7
D0 ACK
Acknowledge
D7
D0
www.ti.com................................................................................................................................................. SLOS598A – MARCH 2009 – REVISED OCTOBER 2009
Figure 34. Multiple-Byte Write Transfer
SINGLE-BYTE READ
As shown in Figure 35, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a 0.
After receiving the TPA6140A2 address and the read/write bit, the TPA6140A2 responds with an acknowledge
bit. The master then sends the internal memory address byte, after which the TPA6140A2 issues an
acknowledge bit. The master device transmits another start condition followed by the TPA6140A2 address and
the read/write bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the TPA6140A2
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
Figure 35. Single-Byte Read Transfer
MULTIPLE-BYTE READ
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TPA6140A2 to the master device as shown in Figure 36. With the exception of the last
data byte, the master device responds with an acknowledge bit after receiving each data byte.
Figure 36. Multiple-Byte Read Transfer
Copyright 2009, Texas Instruments Incorporated
21
Product Folder Link(s): TPA6140A2
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