V
(rms) +
V
O(PP)
2 2
Power +
V
(rms)
2
R
L
(12)
USING LOW-ESR CAPACITORS
RL
2x VO(PP)
VO(PP)
-VO(PP)
VDD
DIFFERENTIAL OUTPUT VERSUS
fc +
1
2p R
L
C
(13)
www.ti.com........................................................................................................................................................ SLOS367C – AUGUST 2003 – REVISED JUNE 2008
lengths between the amplifier and the speaker. For
higher frequency transients, spikes, or digital hash on
the line, a good low equivalent-series-resistance
(ESR) ceramic capacitor, typically 0.1
F to 1 F,
placed as close as possible to the device VDD lead
works best. For filtering lower frequency noise
signals, a 10-
F or greater capacitor placed near the
audio power amplifier also helps, but is not required
in most applications because of the high PSRR of this
device.
Low-ESR capacitors are recommended throughout
this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in
series with an ideal capacitor. The voltage drop
across this resistor minimizes the beneficial effects of
the capacitor in the circuit. The lower the equivalent
value of this resistance the more the real capacitor
behaves like an ideal capacitor.
SINGLE-ENDED OUTPUT
Figure 33. Differential Output Configuration
Figure 33 shows a Class-AB audio power amplifier
(APA)
in
a
fully
differential
configuration.
The
In a typical wireless handset operating at 3.6 V,
TPA6211A1 amplifier has differential outputs driving
bridging raises the power into an 8-
speaker from a
both ends of the load. One of several potential
singled-ended (SE, ground reference) limit of 200
benefits to this configuration is power to the load. The
mW to 800 mW. This is a 6-dB improvement in sound
differential drive to the speaker means that as one
power—loudness that can be heard. In addition to
side is slewing up, the other side is slewing down,
increased
power,
there
are
frequency-response
and vice versa. This in effect doubles the voltage
concerns.
Consider
the
single-supply
SE
swing
on
the
load
as
compared
to
a
configuration
shown
in
A
coupling
ground-referenced load. Plugging 2
VO(PP) into the
capacitor (CC) is required to block the dc-offset
power equation, where voltage is squared, yields
voltage from the load. This capacitor can be quite
4
the output power from the same supply rail and
large (approximately 33
F to 1000 F) so it tends to
be expensive, heavy, occupy valuable PCB area, and
have
the
additional
drawback
of
limiting
low-frequency performance. This frequency-limiting
effect is due to the high-pass filter network created
with
the
speaker
impedance
and
the
coupling
For example, a 68-
F capacitor with an 8- speaker
would attenuate low frequencies below 293 Hz. The
BTL configuration cancels the dc offsets, which
Copyright 2003–2008, Texas Instruments Incorporated
17